Methods of Analysis and Selected Topics(dc)

Methods of Analysis and Selected Topics(dc)

INTRODUCTION
The circuits described in the previous chapters had only one source or two or more sources in series or parallel present. The step-by-step procedure outlined in those chapters cannot be applied if the sources are not in series or parallel. There will be an interaction of sources that will not permit the reduction technique used in Chapter 7 to find quantities such as the total resistance and source current. Methods of analysis have been developed that allow us to approach, in a systematic manner, a network with any number of sources in any arrangement. Fortunately, these methods can also be applied to networks with only one source. The methods to be discussed in detail in this chapter include branch-current analysis, mesh analysis, and nodal analysis. Each can be applied to the same network. The “best” method cannot be defined by a set of rules but can be determined only by acquiring a firm understanding of the relative advantages of each. All the methods can be applied to linear bilateral networks. The term linear indicates that the characteristics of the network elements (such as the resistors) are independent of the voltage across or current through them. The second term, bilateral, refers to the fact that there is no change in the behavior or characteristics of an element if the current through or voltage across the element is reversed. Of the three methods listed above, the branchcurrent method is the only one not restricted to bilateral devices. Before discussing the methods in detail, we shall consider the current source and conversions between voltage and current sources. At the end of the chapter we shall consider bridge networks and D-Y andY-D conversions. Chapter 9 will present the important theorems of network analysis that can also be employed to solve networks with more than one source.
8.2 CURRENT SOURCES
The concept of the current source was introduced in Section 2.4 with the photograph of a commercially available unit. We must now investi
Methods of Analysis and Selected Topics(dc)
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256  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
gate its characteristics in greater detail so that we can properly determine its effect on the networks to be examined in this chapter. The current source is often referred to as the dual of the voltage source. A battery supplies a fixed voltage, and the source current can vary; but the current source supplies a fixed current to the branch in which it is located, while its terminal voltage may vary as determined by the network to which it is applied. Note from the above that duality simply implies an interchange of current and voltage to distinguish the characteristics of one source from the other. The interest in the current source is due primarily to semiconductor devices such as the transistor. In the basic electronics courses, you will find that the transistor is a current-controlled device. In the physical model (equivalent circuit) of a transistor used in the analysis of transistor networks,thereappearsacurrentsourceasindicatedinFig.8.1.Thesymbol for a current source appears in Fig. 8.1(a). The direction of the arrow withinthecircleindicatesthedirectioninwhichcurrentisbeingsupplied.
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For further comparison, the terminal characteristics of an ideal dc voltage and current source are presented in Fig. 8.2, ideal implying perfect sources, or no internal losses sensitive to the demand from the applied load. Note that for the voltage source, the terminal voltage is fixed at E volts independent of the direction of the current I. The direction and magnitude of I will be determined by the network to which the supply is connected.
FIG. 8.1 Current source within the transistor equivalent circuit.
(a) Transistor symbol (b) Transistor equivalent circuit
Current source
βre
C
E
B Ib βIbB C
E
=
FIG. 8.2 Comparing the characteristics of an ideal voltage and current source.
Voltage
E
I
E
0 I
(a)
Current
Vs
I
I
0
(b)
Vs
(+) –
(–) +
I
The characteristics of the ideal current source, shown in Fig. 8.2(b), reveal that the magnitude of the supply current is independent of the polarity of the voltage across the source. The polarity and magnitude of the source voltage Vs will be determined by the network to which the source is connected. For all one-voltage-source networks the current will have the direction indicated to the right of the battery in Fig. 8.2(a). For all single
SOURCE CONVERSIONS  257
current-source networks, it will have the polarity indicated to the right of the current source in Fig. 8.2(b). In review:
A current source determines the current in the branch in which it is located
and
the magnitude and polarity of the voltage across a current source are a function of the network to which it is applied.
EXAMPLE 8.1 Find the source voltage Vs and the current I1 for the circuit of Fig. 8.3.
Solution:
I1 I 10 mA Vs V1 I1R1 (10 mA)(20 k ) 200 V
EXAMPLE 8.2 Find the voltage Vs and the currents I1 and I2 for the network of Fig. 8.4.
Solution:
Vs E 12 V
I2 V R R E R 3 A
Applying Kirchhoff’s current law:
I I1 I2 and I1 I I2 7 A 3 A 4 A
EXAMPLE 8.3 Determine the current I1 and the voltage Vs for the network of Fig. 8.5.
Solution: Using the current divider rule:
I1 2 A
The voltage V1 is
V1 I1R1 (2 A)(2 ) 4 V
and, applying Kirchhoff’s voltage law,
Vs V1 20 V 0 and Vs V1 20 V 4 V 20 V 24 V
Note the polarity of Vs as determined by the multisource network.
8.3 SOURCE CONVERSIONS
The current source described in the previous section is called an ideal source due to the absence of any internal resistance. In reality, all
(1 )(6 A) 1 2
R2I R2 R1
12 V 4
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–
I  =  10 mA
+
R1 20 k
I1
Vs
–
+ V1
FIG. 8.3 Example 8.1.
E R 12 V 4
I1
Vs 7 A + – I
I2
FIG. 8.4 Example 8.2.
+  20 V
2
R1
6 A
–
+
Vs
R2
1
+  V1  –
I
I1
FIG. 8.5 Example 8.3.
258  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
sources—whether they are voltage or current—have some internal resistance in the relative positions shown in Figs. 8.6 and 8.7. For the voltage source, if Rs 0 or is so small compared to any series resistor that it can be ignored, then we have an “ideal” voltage source. For the current source, if Rs ∞ or is large enough compared to other parallel elements that it can be ignored, then we have an “ideal” current source. If the internal resistance is included with either source, then that source can be converted to the other type using the procedure to be described in this section. Since it is often advantageous to make such a maneuver, this entire section is devoted to being sure that the steps are understood. It is important to realize, however, as we proceed through this section, that
source conversions are equivalent only at their external terminals.
The internal characteristics of each are quite different. We want the equivalence to ensure that the applied load of Figs. 8.6 and 8.7 will receive the same current, voltage, and power from each source and in effect not know, or care, which source is present. In Fig. 8.6 if we solve for the load current IL, we obtain
IL Rs E
RL (8.1)
If we multiply this by a factor of 1, which we can choose to be Rs/Rs, we obtain
IL Rs (1 )E RL ( R R s s /Rs R )E L R R s s ( E/R R s L ) Rs R sI RL (8.2) If we define I E/Rs, Equation (8.2) is the same as that obtained by applying the current divider rule to the network of Fig. 8.7. The result is an equivalence between the networks of Figs. 8.6 and 8.7 that simply requires that I E/Rs and the series resistor Rs of Fig. 8.6 be placed in parallel, as in Fig. 8.7. The validity of this is demonstrated in Example 8.4 of this section. For clarity, the equivalent sources, as far as terminals a and b are concerned, are repeated in Fig. 8.8 with the equations for converting in either direction. Note, as just indicated, that the resistor Rs is the same in each source; only its position changes. The current of the current source or the voltage of the voltage source is determined using Ohm’s law and the parameters of the other configuration. It was pointed out in some detail in Chapter 6 that every source of voltage has some internal series resistance. Forthe current source, some internal parallel resistance will always exist in the practical world. However, in many cases, it is an
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Rs
RL
IL
E
Rs
RL
IL
E RsI  =
FIG. 8.6 Practical voltage source.
FIG. 8.7 Practical current source.
a
b
a
b
E  =  IRs
Rs
Rs
I  =
E Rs
FIG. 8.8 Source conversion.
SOURCE CONVERSIONS  259
excellent approximation to drop the internal resistance of a source due to the magnitude of the elements of the network to which it is applied. For this reason, in the analyses to follow, voltage sources may appear without a series resistor, and current sources may appear without a parallel resistance. Realize, however, that for us to perform a conversion from one type of source to another, a voltage source must have a resistor in series with it, and a current source must have a resistor in parallel.
EXAMPLE 8.4 a. Convert the voltage source of Fig. 8.9(a) to a current source, and calculate the current through the 4- load for each source. b. Replace the 4- load with a 1-k load, and calculate the current IL for the voltage source. c. Repeat the calculation of part (b) assuming that the voltage source is ideal (Rs 0 ) because RL is so much larger than Rs. Is this one of those situations where assuming that the source is ideal is an appropriate approximation?
Solutions: a. See Fig. 8.9.
Fig. 8.9(a): IL Rs E
RL 2 6 V 4 1 A
Fig. 8.9(b): IL Rs R sI RL 2 (2 )(3 4 A ) 1 A
b. IL Rs E
RL 5.99 mA
c. IL R E L 6 mA 5.99 mA Yes, RL k Rs (voltage source).
EXAMPLE 8.5 a. Convert the current source of Fig. 8.10(a) to a voltage source, and find the load current for each source. b. Replace the 6-k load with a 10- load, and calculate the current IL for the current source. c. Repeat the calculation of part (b) assuming that the current source is ideal (Rs ∞ ) because RL is so much smaller than Rs. Is this one of those situations where assuming that the source is ideal is an appropriate approximation?
6 V 1 k
6 V 2 1 k
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(a)
Rs
RL
2
–
+
6 V
4
IL
E
a
b
(b)
Rs RL 2 4
IL
a
b
I  = =  3 A E Rs
3 A
FIG. 8.9 Example 8.4.
FIG. 8.10 Example 8.5.
(b)
Rs
RL
3 k
–
+
6 k
ILE  =  IRs  =  27 V
a
b
(a)
Rs RL 3 k 6 k
IL
a
b
9 mA I
9 mA
260  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Solutions: a. See Fig. 8.10.
Fig. 8.10(a): IL Rs R sI RL 3 mA
Fig. 8.10(b): IL Rs E
RL 3 mA
b. IL Rs R sI RL 8.97 mA c. IL I 9 mA 8.97 mA Yes, Rs k RL (current source).
8.4 CURRENT SOURCES IN PARALLEL
If two or more current sources are in parallel, they may all be replaced by one current source having the magnitude and direction of the resultant, which can be found by summing the currents in one direction and subtracting the sum of the currents in the opposite direction. The new parallel resistance is determined by methods described in the discussion of parallel resistors in Chapter 5. Consider the following examples. 
EXAMPLE 8.6 Reduce the parallel current sources of Figs. 8.11 and 8.12 to a single current source.
(3 k )(9 mA) 3 k 10
27 V 9 k
27 V 3 k 6 k
(3 k )(9 mA) 3 k 6 k
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FIG. 8.11 Example 8.6.
FIG. 8.12 Example 8.6.
Is  =  10 A  –  6 A  =  4 A Rs  =  3    6  =  2
6 A
R1 3
10 A
R2 6
4 A R3 2 I s
3 A R1 4 Rs 4 Is7 A 4 A 8 A
Is  =  7 A  +  4 A  –  3 A  =  8 A Rs  =  R1  =  4
Solution: Note the solution in each figure.
BRANCH-CURRENT ANALYSIS  261
EXAMPLE 8.7 Reduce the network of Fig. 8.13 to a single current source, and calculate the current through RL.
Solution: In this example, the voltage source will first be converted to a current source as shown in Fig. 8.14. Combining current sources,
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I2 6 A 24 R2 RL 14
IL
R1 8
E1 32 V
FIG. 8.13 Example 8.7.I 1 4 A 8 R1 24 R2I 2 6 A RL 14 IL
I1  =
E1 R1
=
32 V 8
= 4 A
Is I1 I2 4 A 6 A 10 A and Rs R1 R2 8 24 6
Applying the current divider rule to the resulting network of Fig. 8.15,
IL Rs R sIs RL 3 A
EXAMPLE 8.8 Determine the current I2 in the network of Fig. 8.16.
Solution: Although it might appear that the network cannot be solved using methods introduced thus far, one source conversion as shown in Fig. 8.17 will result in a simple series circuit:
Es I1R1 (4 A)(3 ) 12 V and Rs R1 3
and I2 3.4 A
8.5 CURRENT SOURCES IN SERIES
The current through any branch of a network can be only single-valued. For the situation indicated at point a in Fig. 8.18, we find by application of Kirchhoff’s current law that the current leaving that point is greater than that entering—an impossible situation. Therefore,
current sources of different current ratings are not connected in series,
just as voltage sources of different voltage ratings are not connected in parallel.
8.6 BRANCH-CURRENT ANALYSIS
We will now consider the first in a series of methods for solving networks with two or more sources. Once the branch-current method is
17 V 5
12 V 5 V 3 2
Es E2 Rs R2
60 A 20
(6 )(10 A) 6 14
FIG. 8.14 Network of Fig. 8.13 following the conversion of the voltage source to a current source.
Is 10 A 6 Rs RL 14
IL
Is
FIG. 8.15 Network of Fig. 8.14 reduced to its simplest form.
I1 4 A 3 R1 R2 2
I2
5 V
a
b
E2 –+
FIG. 8.16 Example 8.8.
E2
3
–+
Rs
Es 12 V
2 R 2
5 V
I2+
–
a
b
FIG. 8.17 Network of Fig. 8.16 following the conversion of the current source to a voltage source.
a6 A 7 A
No!
FIG. 8.18 Invalid situation.
(a) (b)
12 123 12
3 1
2
3
262  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
mastered, there is no linear dc network for which a solution cannot be found. Keep in mind that networks with two isolated voltage sources cannot be solved using the approach of Chapter 7. For additional evidence of this fact, try solving for the unknown elements of Example 8.9 using the methods introduced in Chapter 7. The network of Fig. 8.21 can be solved using the source conversions described in the last section, but the method to be described in this section has applications far beyond the configuration of this network. The most direct introduction to a method of this type is to list the series of steps required for its application. There are four steps, as indicated below. Before continuing, understand that this method will produce the current through each branch of the network, the branch current. Once this is known, all other quantities, such as voltage or power, can be determined.
1. Assign a distinct current of arbitrary direction to each branch of the network. 2. Indicate the polarities for each resistor as determined by the assumed current direction. 3. Apply Kirchhoff’s voltage law around each closed, independent loop of the network.
The best way to determine how many times Kirchhoff’s voltage law will have to be applied is to determine the number of “windows” in the network. The network of Example 8.9 has a definite similarity to the two-window configuration of Fig. 8.19(a). The result is a need to apply Kirchhoff’s voltage law twice. For networks with three windows, as shown in Fig. 8.19(b), three applications of Kirchhoff’s voltage law are required, and so on.
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4. Apply Kirchhoff’s current law at the minimum number of nodes that will include all the branch currents of the network.
The minimum number is one less than the number of independent nodes of the network. For the purposes of this analysis, a node is a junction of two or more branches, where a branch is any combination
FIG. 8.19 Determining the number of independent closed loops.
(4 nodes)
2
3
4
1 4 – 1  =  3 eq.
(4 nodes)
234
1 4 – 1  =  3 eq.
(2 nodes) 2
1 2 – 1  =  1 eq.
(2 nodes) 2
1 2 – 1  =  1 eq.
FIG. 8.20 Determining the number of applications of Kirchhoff’s current law required.
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4
6 V
I1
E2
–
+
1
2 VE 1 – +
2 R 1
I2
I3
bd
a
c
R2
R3
FIG. 8.21 Example 8.9.Defined by I1 I2
4
6 V
–
a
+ 21
I1
E2
–
+
–
+ 1
2 VE 1 – +
–
+ 2
I3
Defined by I2
Fixed polarity
Fixed polarity
Defined by I3
FIG. 8.22 Inserting the polarities across the resistive elements as defined by the chosen branch currents.
Step 3: Kirchhoff’s voltage law is applied around each closed loop (1 and 2) in the clockwise direction:
and
of series elements. Figure 8.20 defines the number of applications of Kirchhoff’s current law for each configuration of Fig. 8.19.
5. Solve the resulting simultaneous linear equations for assumed branch currents.
It is assumed that the use of the determinants method to solve for the currents I1, I2, and I3 is understood and is a part of the student’s mathematical background. If not, a detailed explanation of the procedure is provided in Appendix C. Calculators and computer software packages such as Mathcad can find the solutions quickly and accurately.
EXAMPLE 8.9 Apply the branch-current method to the network of Fig. 8.21.
Solution 1:
Step 1: Since there are three distinct branches (cda, cba, ca), three currents of arbitrary directions (I1, I2, I3) are chosen, as indicated in Fig. 8.21. The current directions for I1 and I2 were chosen to match the “pressure” applied by sources E1 and E2, respectively. Since both I1 and I2 enter node a, I3 is leaving.
Step 2: Polarities for each resistor are drawn to agree with assumed current directions, as indicated in Fig. 8.22.
loop 1:  V E1 VR1 VR3 0
Rise in potential
Drop in potential
loop 2:  V VR3 VR2 E2   0
Rise in potential
Drop in potential loop 1:  V 2 V  2 I1  4 I3 0 
loop 2:  V  4 I3  1 I2 6 V 0 
Battery potential
Voltage drop across 2- resistor
Voltage drop across 4- resistor




264  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Step 4: Applying Kirchhoff’s current law at node a (in a two-node network, the law is applied at only one node), I1 I2 I3
Step 5: There are three equations and three unknowns (units removed for clarity): 2 2I1 4I3 0R e written: 2I1 0 4I3 2 4I3 1I2 6 0 0 I2 4I3 6 I1 I2 I3 I1 I2 I3 0
Using third-order determinants (Appendix C), we have
Mathcad Solution: Once you understand the procedure for entering the parameters, you can use Mathcad to solve determinants such as
2        0        4       6        1        4       
2        0        4       0        1        4       
0        1                   1
1        1                   1
2        2              4 0        6              4
2        0              2 0        1              6 1        1              0
1        0     1
I1
I2
I3
D
1 A
2 A
1 A
D
D
A negative sign in front of a branch current indicates only that the actual current is in the direction opposite to that assumed.
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FIG. 8.23 Using Mathcad to verify the numerical calculations of Example 8.9.
BRANCH-CURRENT ANALYSIS  265
appearing in Solution 1 in a very short time frame. The numerator is defined by n in the same manner described for earlier exercises. Then the sequence View-Toolbars-Matrix is applied to obtain the Matrix toolbar appearing in Fig. 8.23. Selecting the top left option called Matrix will result in the Insert Matrix dialog box in which 3 3 is selected. The 3 3 matrix will appear with a bracket to signal which parameter should be entered. Enter that parameter, and then use the left click of the mouse to select the next parameter you want to enter. When you have finished, move on to define the denominator d in the same manner. Then define the current of interest, select Determinant from the Matrix toolbar, and insert the numerator variable n. Follow with a division sign, and enter the Determinant of the denominator as shown in Fig. 8.23. Retype I1 and select the equal sign; the correct result of 1 will appear. Once you have mastered the rather simple and direct process just described, the availability of Mathcad as a checking tool or solving mechanism will be deeply appreciated.
Solution 2: Instead of using third-order determinants as in Solution 1, we could reduce the three equations to two by substituting the third equation in the first and second equations:
or 6I1 4I2 2 4I1 5I2 6
Multiplying through by 1 in the top equation yields
6I1 4I2 2 4I1 5I2 6
and using determinants, 24 65 10 24 14 I1 ––––––– –––––––– ––––   1A 64 30 16 14 45
Using the TI-86 calculator:
CALC. 8.1
Note the det (determinant) obtained from a Math listing under a MATRX menu and the fact that each determinant must be determined individually. The first set of brackets within the overall determinant brackets of the first determinant defines the first row of the determinant, while the second set of brackets within the same determinant defines the second row. A comma separates the entries for each row. Obviously, the time to learn how to enter the parameters is minimal when you consider the savings in time and the accuracy obtained.
2 2I1 4  I1 I2   0 2 2I1 4I1 4I2   0
4  I1 I2   I2 6 0 4I1 4I2 I2 6 0  
I3
I3
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det[[2,4][6,5]]/det[[6,4][4,5]] ENTER 1
266  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
62 46 36 8 28 I2 ––––––– –––––– – –– 2 A 14 14 14
I3 I1 I2 1 2 1 A
It is now important that the impact of the results obtained be understood. The currents I1, I2, and I3 are the actual currents in the branches in which they were defined. A negative sign in the solution simply reveals that the actual current has the opposite direction than initially defined—the magnitude is correct. Once the actual current directions and their magnitudes are inserted in the original network, the various voltages and power levels can be determined. For this example, the actual current directions and their magnitudes have been entered on the original network in Fig. 8.24. Note that the current through the series elements R1 and E1 is 1 A; the current through R3, 1 A; and the current through the series elements R2 and E2, 2 A. Due to the minus sign in the solution, the direction of I1 is opposite to that shown in Fig. 8.21. The voltage across any resistor can now be found using Ohm’s law, and the power delivered by either source or to any one of the three resistors can be found using the appropriate power equation.
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Applying Kirchhoff’s voltage law around the loop indicated in Fig. 8.24,
V (4 )I3 (1 )I2 6 V 0 or (4 )I3 (1 )I2 6 V
and (4 )(1 A) (1 )(2 A) 6 V 4 V 2 V 6 V 6 V 6 V (checks)
EXAMPLE 8.10 Apply branch-current analysis to the network of Fig. 8.25.
Solution: Again, the current directions were chosen to match the “pressure” of each battery. The polarities are then added and Kirchhoff’s voltage law is applied around each closed loop in the clockwise direction. The result is as follows:
loop 1: 15 V (4 )I1 (10 )I3 20 V 0 loop 2: 20 V (10 )I3 (5 )I2 40 V 0

4
6 V
–
+
I1  =  1 A
E2
–
+
–
+ 1
2 VE 1 – +
–
+
2
R3
R1 R2 I2  =  2 A
I3  =  1 A
FIG. 8.24 Reviewing the results of the analysis of the network of Fig. 8.21.
MESH ANALYSIS (GENERAL APPROACH)  267
Applying Kirchhoff’s current law at node a,
I1 I3 I2
Substituting the third equation into the other two yields (with units removed for clarity) 15 4I1 10I3 20 0 Substituting for I2 (since it occurs20 10I3 5(I1 I3) 40 0 only once in the two equations)
or 4I1 10I3 5 5I1 15I3 60
Multiplying the lower equation by 1, we have
4I1 10I3 5 5I1 15I3 60
5 10 60 15 75 600 525 I1 –––––––– ––––––––– ––––– 4.773 A 4 10 60 50 110 5 15 45 5 60 240 25 265 I3 –––––––– –––––––—–– ––—– 2.409 A 110 110 110
I2 I1 I3 4.773 2.409 7.182 A
revealing that the assumed directions were the actual directions, with I2 equal to the sum of I1 and I3.
8.7 MESH ANALYSIS (GENERAL APPROACH)
The second method of analysis to be described is called mesh analysis. The term mesh is derived from the similarities in appearance between the closed loops of a network and a wire mesh fence. Although this approach is on a more sophisticated plane than the branch-current method, it incorporates many of the ideas just developed. Of the two methods, mesh analysis is the one more frequently applied today. Branch-current analysis is introduced as a stepping stone to mesh analysis because branch currents are initially more “real” to the student than the mesh (loop) currents employed in mesh analysis. Essentially,
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I1 5 R 1
I2
I3
a
R2R 3 10
+
–+
–
4
40 VE 2 + –
15 VE 1 – +
20 VE 3 – +
21
–
+
FIG. 8.25 Example 8.10.
268  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
the mesh-analysis approach simply eliminates the need to substitute the results of Kirchhoff’s current law into the equations derived from Kirchhoff’s voltage law. It is now accomplished in the initial writing of the equations. The systematic approach outlined below should be followed when applying this method.
1. Assign a distinct current in the clockwise direction to each independent, closed loop of the network. It is not absolutely necessary to choose the clockwise direction for each loop current. In fact, any direction can be chosen for each loop current with no loss in accuracy, as long as the remaining steps are followed properly. However, by choosing the clockwise direction as a standard, we can develop a shorthand method (Section 8.8) for writing the required equations that will save time and possibly prevent some common errors.
This first step is accomplished most effectively by placing a loop current within each “window” of the network, as demonstrated in the previous section, to ensure that they are all independent. A variety of other loop currents can be assigned. In each case, however, be sure that the information carried by any one loop equation is not included in a combination of the other network equations. This is the crux of the terminology: independent. No matter how you choose your loop currents, the number of loop currents required is always equal to the number of windows of a planar (no-crossovers) network. On occasion a network may appear to be nonplanar. However, a redrawing of the network may reveal that it is, in fact, planar. Such may be the case in one or two problems at the end of the chapter. Before continuing to the next step, let us ensure that the concept of a loop current is clear. For the network of Fig. 8.26, the loop current I1 is the branch current of the branch containing the 2- resistor and 2-V battery. The current through the 4- resistor is not I1, however, since there is also a loop current I2 through it. Since they have opposite directions, I4 equals the difference between the two, I1 I2 or I2 I1, depending on which you choose to be the defining direction. In other words, a loop current is a branch current only when it is the only loop current assigned to that branch.
2. Indicate the polarities within each loop for each resistor as determined by the assumed direction of loop current for that loop. Note the requirement that the polarities be placed within each loop. This requires, as shown in Fig. 8.26, that the 4- resistor have two sets of polarities across it. 3. Apply Kirchhoff’s voltage law around each closed loop in the clockwise direction. Again, the clockwise direction was chosen to establish uniformity and prepare us for the method to be introduced in the next section. a. If a resistor has two or more assumed currents through it, the total current through the resistor is the assumed current of the loop in which Kirchhoff’s voltage law is being applied, plus the assumed currents of the other loops passing through in the same direction, minus the assumed currents through in the opposite direction. b. The polarity of a voltage source is unaffected by the direction of the assigned loop currents. 4. Solve the resulting simultaneous linear equations for the assumed loop currents.
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FIG. 8.26 Defining the mesh currents for a “twowindow” network.
I1
1 R 1
I2
R2
+
–+
–
2
6 V E2 + –2 VE 1 – +
21 R3 4 + – – +
I3
MESH ANALYSIS (GENERAL APPROACH)  269
EXAMPLE 8.11 Consider the same basic network as in Example 8.9 of the preceding section, now appearing in Fig. 8.26.
Solution:
Step 1: Two loop currents (I1 and I2) are assigned in the clockwise direction in the windows of the network. A third loop (I3) could have been included around the entire network, but the information carried by this loop is already included in the other two.
Step 2: Polarities are drawn within each window to agree with assumed current directions. Note that for this case, the polarities across the 4- resistor are the opposite for each loop current.
Step 3: Kirchhoff’s voltage law is applied around each loop in the clockwise direction. Keep in mind as this step is performed that the law is concerned only with the magnitude and polarity of the voltages around the closed loop and not with whether a voltage rise or drop is due to a battery or a resistive element. The voltage across each resistor is determined by V IR, and for a resistor with more than one current through it, the current is the loop current of the loop being examined plus or minus the other loop currents as determined by their directions. If clockwise applications of Kirchhoff’s voltage law are always chosen, the other loop currents will always be subtracted from the loop current of the loop being analyzed.
loop 1: E1 V1 V3 0 (clockwise starting at point a)
loop 2: V3 V2 E2 0 (clockwise starting at point b) (4 )(I2 I1) (1 )I2 6 V 0
Step 4: The equations are then rewritten as follows (without units for clarity):
loop 1: 2 2I1 4I1 4I2 0 loop 2: 4I2 4I1 1I2 6 0 and loop 1: 2 6I1 4I2 0 loop 2: 5I2 4I1 6 0 or loop 1: 6I1 4I2 2 loop 2: 4I1 5I2 6
Applying determinants will result in
I1 1 A and I2 2 A
The minus signs indicate that the currents have a direction opposite to that indicated by the assumed loop current. The actual current through the 2-V source and 2- resistor is therefore 1 A in the other direction, and the current through the 6-V source and 1- resistor is 2 A in the opposite direction indicated on the circuit. The current through the 4- resistor is determined by the following equation from the original network:
2 V  2  I1  4   I1 I2   0 
Total current through 4- resistor
Voltage drop across 4- resistor
Subtracted since I
2
 is opposite in direction to I 1
.
NA
270  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
loop 1: I4 I1 I2 1 A ( 2 A) 1 A 2 A 1 A (in the direction of I1)
The outer loop (I3) and one inner loop (either I1 or I2) would also have produced the correct results. This approach, however, will often lead to errors since the loop equations may be more difficult to write. The best method of picking these loop currents is to use the window approach.
EXAMPLE 8.12 Find the current through each branch of the network of Fig. 8.27.
Solution:
Steps 1 and 2 are as indicated in the circuit. Note that the polarities of the 6- resistor are different for each loop current.
Step 3: Kirchhoff’s voltage law is applied around each closed loop in the clockwise direction:
loop 1: E1 V1 V2 E2 0 (clockwise starting at point a) 5 V (1 )I1 (6 )(I1 I2) 10 V 0
I2 flows through the 6-Q resistor in the direction opposite to I1.
loop 2: E2 V2 V3 0 (clockwise starting at point b) 10 V (6 )(I2 I1) (2 )I2 0
The equations are rewritten as 5 I1 6I1 6I2 10 0 7I1 6I2 5 10 6I2 6I1 2I2 0 6I1 8I2 10 Step 4: 56 10 8 40 60 20 I1 –––––––––– ––––––––– –– – 1 A 76 56 36 20 6 8 75 6 10 70 30 40 I2 –––––––––– ––––––– –– 2 A 20 20 20
Since I1 and I2 are positive and flow in opposite directions through the 6- resistor and 10-V source, the total current in this branch is equal to the difference of the two currents in the direction of the larger:
I2 > I1 (2 A > 1 A)
Therefore,
IR2 I2 I1 2A 1A 1A in the direction of I2
It is sometimes impractical to draw all the branches of a circuit at right angles to one another. The next example demonstrates how a portion of a network may appear due to various constraints. The method of analysis does not change with this change in configuration.
NA
R1 R2 6 + – 1
5 VE 1 – +
10 VE 2 – +
21
+
–
a
2
I2
+
–
–
+
b
I1
R3
FIG. 8.27 Example 8.12.
MESH ANALYSIS (GENERAL APPROACH)  271
6 10 4 1 6 40 34 I2 ––––––– –––––––– –––– 0.773 A 44 44 44
The current in the 4- resistor and 4-V source for loop 1 is I1 I2 2.182 A ( 0.773 A) 2.182 A 0.773 A 1.409 A
revealing that it is 1.409 A in a direction opposite (due to the minus sign) to I1 in loop 1.
Supermesh Currents
On occasion there will be current sources in the network to which mesh analysis is to be applied. In such cases one can convert the current source to a voltage source (if a parallel resistor is present) and proceed as before or utilize a supermesh current and proceed as follows. Start as before and assign a mesh current to each independent loop, including the current sources, as if they were resistors or voltage sources. Then mentally (redraw the network if necessary) remove the current sources (replace with open-circuit equivalents), and apply
NA
a
R1 = 2
2
+
–
E2 4 V
R3 = 6 –
+
E1 = 6 V +
– +
–
b I1 I2
E3 = 3 V
12 R2 4 + – – +
FIG. 8.28 Example 8.13.
det[[ 10, 4][ 1, 10]]/det[[6, 4][4, 10]] ENTER 2.182
CALC. 8.2
EXAMPLE 8.13 Find the branch currents of the network of Fig. 8.28.
Solution:
Steps 1 and 2 are as indicated in the circuit.
Step 3: Kirchhoff’s voltage law is applied around each closed loop:
loop 1: E1 I1R1 E2 V2 0 (clockwise from point a) 6 V (2 )I1 4 V (4 )(I1 I2) 0 loop 2: V2 E2 V3 E3 0 (clockwise from point b) (4 )(I2 I1) 4 V (6 )(I2) 3 V 0
which are rewritten as 10 4I1 2I1 4I2 0 6I1 4I2 10 1 4I1 4I2 6I2 0 4I1 10I2 1
or, by multiplying the top equation by 1, we obtain
6I1 4I2 10 4I1 10I2 1
Step 4: 10 4   1 10 100 4 96 I1 ––––––––––– ––––––––– –––– 2.182 A 6 4 60 16 44 4 10
Using the TI-86 calculator:
272  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Kirchhoff’s voltage law to all the remaining independent paths of the network using the mesh currents just defined. Any resulting path, including two or more mesh currents, is said to be the path of a supermesh current. Then relate the chosen mesh currents of the network to the independent current sources of the network, and solve for the mesh currents. The next example will clarify the definition of a supermesh current and the procedure.
EXAMPLE 8.14 Using mesh analysis, determine the currents of the network of Fig. 8.29.
NA
Solution: First, the mesh currents for the network are defined, as shown in Fig. 8.30. Then the current source is mentally removed, as shown in Fig. 8.31, and Kirchhoff’s voltage law is applied to the resulting network. The single path now including the effects of two mesh currents is referred to as the path of a supermesh current.
R1 6
E1 20 V
E2 12 V4 AI
R2
4
R3
2
FIG. 8.29 Example 8.14.
R1 6
E1 20 V
E2 12 V4 AI
R2
4
R3
2
I1 I2
a
FIG. 8.30 Defining the mesh currents for the network of Fig. 8.29.
E1 20 V
E2 12 VI 1 I2
+ – + –
+
–
R2
4
R3
2
R1 6
Supermesh current
FIG. 8.31 Defining the supermesh current.
Applying Kirchhoff’s law:
20 V I1(6 ) I1(4 ) I2(2 ) 12 V 0 or 10I1 2I2 32
MESH ANALYSIS (GENERAL APPROACH)  273
Node a is then used to relate the mesh currents and the current source using Kirchhoff’s current law:
I1 I I2
The result is two equations and two unknowns:
10I1 2I2 32 I1 I2 4
Applying determinants: 32 2 4 1 (32)( 1) (2)(4) 40 I1 –––––––– ––––––––––––––– ––– 3.33 A 10 2 (10)( 1) (2)(1) 12 1 1
and I2 I1 I 3.33 A 4 A 0.67 A
In the above analysis, it might appear that when the current source was removed, I1 I2. However, the supermesh approach requires that we stick with the original definition of each mesh current and not alter those definitions when current sources are removed.
EXAMPLE 8.15 Using mesh analysis, determine the currents for the network of Fig. 8.32.
NA
I1 I3 I22 8
6
6 A 8 A
FIG. 8.33 Defining the mesh currents for the network of Fig. 8.32.
Supermesh current
I1 I3 I22 8
6 +–
+
–
–
+
FIG. 8.34 Defining the supermesh current for the network of Fig. 8.32.
2 8
6
6 A 8 A
FIG. 8.32 Example 8.15.
Solution: The mesh currents are defined in Fig. 8.33. The current sources are removed, and the single supermesh path is defined in Fig. 8.34.
Applying Kirchhoff’s voltage law around the supermesh path:
V2 V6 V8 0 (I2 I1)2 I2(6 ) (I2 I3)8 0 2I2 2I1 6I2 8I2 8I3 0 2I1 16I2 8I3 0
274  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
NA
Introducing the relationship between the mesh currents and the current sources:
I1 6 A I3 8 A
results in the following solutions:
2I1 16I2 8I3 0 2(6 A) 16I2 8(8 A) 0
and I2 4.75 A
Then I2 I1 I2 6 A 4.75 A 1.25 A and I8 I3 I2 8 A 4.75 A 3.25 A
Again, note that you must stick with your original definitions of the various mesh currents when applying Kirchhoff’s voltage law around the resulting supermesh paths.
8.8 MESH ANALYSIS (FORMAT APPROACH)
Now that the basis for the mesh-analysis approach has been established, we will now examine a technique for writing the mesh equations more rapidly and usually with fewer errors. As an aid in introducing the procedure, the network of Example 8.12 (Fig. 8.27) has been redrawn in Fig. 8.35 with the assigned loop currents. (Note that each loop current has a clockwise direction.) The equations obtained are
7I1 6I2 5 6I1 8I2 10
which can also be written as
7I1 6I2 5 8I2 6I1 10
and expanded as
Col. 1 Col. 2 Col. 3 (1 6)I1 6I2 (5 10) (2 6)I2 6I1 10
Note in the above equations that column 1 is composed of a loop current times the sum of the resistors through which that loop current passes. Column 2 is the product of the resistors common to another loop current times that other loop current. Note that in each equation, this column is subtracted from column 1. Column 3 is the algebraic sum of the voltage sources through which the loop current of interest passes. A source is assigned a positive sign if the loop current passes from the negative to the positive terminal, and a negative value is assigned if the polarities are reversed. The comments above are correct only for a standard direction of loop current in each window, the one chosen being the clockwise direction. The above statements can be extended to develop the following format approach to mesh analysis:
76 A 16
I1 I2
21 2 R3 + –
– R1 +
1 R2 6 + – – +
5 VE 1 – +
10 VE 2 – +
FIG. 8.35 Network of Fig. 8.27 redrawn with assigned loop currents.
MESH ANALYSIS (FORMAT APPROACH)  275
1. Assign a loop current to each independent, closed loop (as in the previous section) in a clockwise direction. 2. The number of required equations is equal to the number of chosen independent, closed loops. Column 1 of each equation is formed by summing the resistance values of those resistors through which the loop current of interest passes and multiplying the result by that loop current. 3. Wemustnowconsiderthemutualterms,which,asnotedinthe examplesabove,arealwayssubtractedfromthefirstcolumn. A mutualtermissimplyanyresistiveelementhavinganadditional loopcurrentpassingthroughit.Itispossibletohavemorethanone mutualtermiftheloopcurrentofinteresthasanelementincommon withmorethanoneotherloopcurrent.Thiswillbedemonstratedin anexampletofollow.Eachtermistheproductofthemutualresistor andtheotherloopcurrentpassingthroughthesameelement. 4. The column to the right of the equality sign is the algebraic sum of the voltage sources through which the loop current of interest passes. Positive signs are assigned to those sources of voltage having a polarity such that the loop current passes from the negative to the positive terminal. A negative sign is assigned to those potentials for which the reverse is true. 5. Solve the resulting simultaneous equations for the desired loop currents.
Before considering a few examples, be aware that since the column to the right of the equals sign is the algebraic sum of the voltage sources in that loop, the format approach can be applied only to networks in which all current sources have been converted to their equivalent voltage source.
EXAMPLE 8.16 Write the mesh equations for the network of Fig. 8.36, and find the current through the 7- resistor.
Solution:
Step 1: As indicated in Fig. 8.36, each assigned loop current has a clockwise direction.
Steps 2 to 4:
I1: (8 6 2 )I1 (2 )I2 4 V I2: (7 2 )I2 (2 )I1 9 V
and 16I1 2I2 4 9I2 2I1 9
which, for determinants, are
16I1 2I2 4 2I1 9I2 9
16 4 2 9 144 8 136 and I2 I7 ––––––––– ––––––––– ––––– 16 2 144 4 140 29 0.971 A
NA
I1 I2
21
4 V –+
6 –+
–
+ 8 7 + – 2 + – – +
9 V +–
FIG. 8.36 Example 8.16.
276  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Solution:
Step 1: Each window is assigned a loop current in the clockwise direction:
Summing terms yields
2I1 I2 0 2 6I2 I1 3I3 4 7I3 3I2 0 2
which are rewritten for determinants as
Note that the coefficients of the a and b diagonals are equal. This symmetry about the c-axis will always be true for equations written using the format approach. It is a check on whether the equations were obtained correctly.
We will now consider a network with only one source of voltage to point out that mesh analysis can be used to advantage in other than multisource networks.
   2I1       I2      0         2
       0           3I2     7I3     2
      I1        6I2       3I3     4
c ba
b
a
1 1  I1  1  I2 0 2 V 4 V 
3 4  I3  3  I2 0 2 V 1 2 3  I2   1  I1   3  I3 4 V    
I1 : I2 : I3 :
I
1
 does not pass through an element mutual with I 3 .
I
3
 does not pass through an element mutual with I 1 .
NA
I1 I2
21
1
+
–
–
+
4 V
–
+
–
+
+
–
–
2 V
+
+
– 1
+
2 V
–
–
+ 4
3 3
2 + –
I3
FIG. 8.37 Example 8.17.
EXAMPLE 8.17 Write the mesh equations for the network of Fig. 8.37.
MESH ANALYSIS (FORMAT APPROACH)  277
Solution 1:
I1: (8 3 )I1 (8 )I3 (3 )I2 15 V I2: (3 5 2 )I2 (3 )I1 (5 )I3 0 I3: (8 10 5 )I3 (8 )I1 (5 )I2 0
11I1 8I3 3I2 15 10I2 3I1 5I3 0 23I3 8I1 5I2 0
or 11I1 3I2 8I3 15 3I1 10I2 5I3 0 8I1 5I2 23I3 0 11 3 15 3 10 0 8 50 and I3 I10 ––––––––––––– 1.220 A 11 3 8 3 10 5 8 5 23
Mathcad Solution: For this example, rather than take the time to develop the determinant form for each variable, we will apply Mathcad directly to the resulting equations. As shown in Fig. 8.39, a Guess value for each variable must first be defined. Such guessing helps the computer begin its iteration process as it searches for the solution. By providing a rough estimate of 1, the computer recognizes that the result will probably be a number with a magnitude less than 100 rather than have to worry about solutions that extend into the thousands or tens of thousands—the search has been narrowed considerably. Next, as shown, the word Given must be entered to tell the computer that the defining equations will follow. Finally, each equation must be carefully entered and set equal to the constant on the right using the Ctrl operation. The results are then obtained with the Find(I1,I2,I3) expression and an equal sign. As shown, the results are available with an acceptable degree of accuracy even though entering the equations and performing the analysis took only a minute or two (with practice).
NA
I1 I2 21 2 + – 3 + – – +
–+ +–
+
–
15 V
–+ +–
10 –+
3
I3
I10 = I3
8 5
FIG. 8.38 Example 8.18.
EXAMPLE 8.18 Find the current through the 10- resistor of the network of Fig. 8.38.
278  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
NA
det[[11, 3,15][ 3,10,0][ 8, 5,0]]/det[[11, 3, 8][ 3,10, 5][ 8, 5,23]] ENTER 1.220
CALC. 8.3
Solution 2: Using the TI-86 calculator:
FIG. 8.39 Using Mathcad to verify the numerical calculations of Example 8.18.
This display certainly requires some care in entering the correct sequence of brackets in the required format, but it is still a rather neat, compact format.
8.9 NODAL ANALYSIS (GENERAL APPROACH)
Recall from the development of loop analysis that the general network equations were obtained by applying Kirchhoff’s voltage law around each closed loop. We will now employ Kirchhoff’s current law to develop a method referred to as nodal analysis. A node is defined as a junction of two or more branches. If we now define one node of any network as a reference (that is, a point of zero potential or ground), the remaining nodes of the network will all have a fixed potential relative to this reference. For a network of N nodes, therefore, there will exist (N 1) nodes with a fixed potential relative to the assigned reference node. Equations relating these nodal voltages can be written by applying Kirchhoff’s current law at each of the (N 1) nodes. To obtain the complete solution of a network, these nodal voltages are then evaluated in the same manner in which loop currents were found in loop analysis.
NODAL ANALYSIS (GENERAL APPROACH)  279
NA
The nodal analysis method is applied as follows:
1. Determine the number of nodes within the network. 2. Pick a reference node, and label each remaining node with a subscripted value of voltage: V1, V2, and so on. 3. Apply Kirchhoff’s current law at each node except the reference. Assume that all unknown currents leave the node for each application of Kirchhoff’s current law. In other words, for each node, don’t be influenced by the direction that an unknown current for another node may have had. Each node is to be treated as a separate entity, independent of the application of Kirchhoff’s current law to the other nodes. 4. Solve the resulting equations for the nodal voltages.
A few examples will clarify the procedure defined by step 3. It will initially take some practice writing the equations for Kirchhoff’s current law correctly, but in time the advantage of assuming that all the currents leave a node rather than identifying a specific direction for each branch will become obvious. (The same type of advantage is associated with assuming that all the mesh currents are clockwise when applying mesh analysis.)
EXAMPLE 8.19 Apply nodal analysis to the network of Fig. 8.40.
Solution:
Steps 1 and 2: The network has two nodes, as shown in Fig. 8.41. The lower node is defined as the reference node at ground potential (zero volts), and the other node as V1, the voltage from node 1 to ground.
Step 3: I1 and I2 are defined as leaving the node in Fig. 8.42, and Kirchhoff’s current law is applied as follows:
I I1 I2
The current I2 is related to the nodal voltage V1 by Ohm’s law:
I2
The current I1 is also determined by Ohm’s law as follows:
I1
with VR1 V1 E Substituting into the Kirchhoff’s current law equation:
I
and rearranging, we have
I V1 or V1 I E R1 1 R2 1 R1
E R1
1 R2
1 R1
V1 R2
E R1
V1 R1
V1 R2
V1 E R1
VR1 R1
V1 R2
VR2 R2
I 1 A12 R 2
R1 6
E 24 V – +
FIG. 8.40 Example 8.19.
I 1 A12 R 2
R1 6
E 24 V
V1
(0 V)
FIG. 8.41 Network of Fig. 8.40 with assigned nodes.
+
–
I 1 A12 R 2
R1 6
E 24 V
V1
(0 V)
I1
–
+ I2
FIG. 8.42 Applying Kirchhoff’s current law to the node V1.
280  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Substituting numerical values, we obtain V1 1 A 4 A 1 A 24 V 6 1 12 1 6
NA
R2
R1
4
R3
E 64 V
8
2 A
I
10
FIG. 8.43 Example 8.20.
R2
R1
4
R3
E 64 V
8
2 A
I
10
+
–
V2V 1
FIG. 8.44 Defining the nodes for the network of Fig. 8.43.
R2
R1
4
R3
E 64 V
8
2 A
I
10
+–
+
–
V2V 1
I1
I2
FIG. 8.45 Applying Kirchhoff’s current law to node V1.
R2
R1
4
R3
E 64 V
8
2 A
I
10
+–
+
–
V2V 1
I3
I2
FIG. 8.46 Applying Kirchhoff’s current law to node V2.
V1 5 A V1 20 V
The currents I1 and I2 can then be determined using the preceding equations:
I1
0.667 A
The minus sign indicates simply that the current I1 has a direction opposite to that appearing in Fig. 8.42.
I2 1.667 A
EXAMPLE 8.20 Apply nodal analysis to the network of Fig. 8.43.
Solution 1:
Steps 1 and 2: The network has three nodes, as defined in Fig. 8.44, with the bottom node again defined as the reference node (at ground potential, or zero volts), and the other nodes as V1 and V2.
Step 3: For node V1 the currents are defined as shown in Fig. 8.45, and Kirchhoff’s current law is applied:
0 I1 I2 I
with I1
and I2
so that I 0
or I 0 and V1 V2 I
Substituting values: V1 V2 2 A 6 A
For node V2 the currents are defined as shown in Fig. 8.46, and Kirchhoff’s current law is applied:
I I2 I3
with I V2 R3 V2 V1 R2
64 V 8
1 4
1 4
1 8
E R1
1 R2
1 R2
1 R1
V2 R2
V1 R2
E R1
V1 R1
V1 V2 R2
V1 E R1
V1 V2 R2
VR2 R2
V1 E R1
20 V 12
V1 R2
4V 6
20 V 24 V 6
V1 E R1
1 4
NODAL ANALYSIS (GENERAL APPROACH)  281
or I and V2 V1 I
Substituting values: V2 V1 2 A
Step 4: The result is two equations and two unknowns: V1 V2 6 A V1 V2 2 A
which become
0.375V1 0.25V2 6 0.25V1 0.35V2 2
Using determinants,
V1 37.818 V V2 32.727 V
Since E is greater than V1, the current I1 flows from ground to V1 and is equal to
IR1 3.273 A
The positive value for V2 results in a current IR3 from node V2 to ground equal to
IR3 3.273 A
Since V1 is greater than V2, the current IR2 flows from V1 to V2 and is equal to
IR2 1.273 A
Mathcad Solution: For this example, we will use Mathcad to work directly with the Kirchhoff’s current law equations rather than taking the mathematical process down the line to more familiar forms. Simply define everything correctly, provide the Guess values, and insert Given where required. The process should be quite straightforward. Note in Fig. 8.47 that the first equation comes from the fact that I1 I2 I 0 while the second equation comes from I2 I3 I. Pay particular attention to the fact that the first equation is defined by Fig. 8.45 and the second by Fig. 8.46 because the direction of I2 is different for each. The results of V1 37.82 V and V2 32.73 V confirm the theoretical solution.
37.818 V 32.727 V 4
V1 V2 R2
32.727 V 10
V2 R3
VR3 R3
64 V 37.818 V 8
E V1 R1
1 10
1 4
1 4
1 4
1 4
1 8
1 4
1 10
1 4
1 R2
1 R3
1 R2
V2 R3
V1 R2
V2 R2
NA
282  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
EXAMPLE 8.21 Determine the nodal voltages for the network of Fig. 8.48.
NA
4 A 2 R1 R2 6
R3
2 A
12
FIG. 8.48 Example 8.21.
4 A
R1 2 A 2
I3
Reference
V1 V2
R2 6
R3  =  12
I1
FIG. 8.49 Defining the nodes and applying Kirchhoff’s current law to the node V1.
Solution:
Steps 1 and 2: As indicated in Fig. 8.49.
FIG. 8.47 Using Mathcad to verify the mathematical calculations of Example 8.20.
NODAL ANALYSIS (GENERAL APPROACH)  283
NA
4 A R1 2 A 2
I3
Reference
V1 V2
R2 6 R3  =  12
I2
FIG. 8.50 Applying Kirchhoff’s current law to the node V2.
Step 3: Included in Fig. 8.49 for the node V1. Applying Kirchhoff’s current law: 4 A I1 I3
and 4 A
Expanding and rearranging: V1 V2 4 A For node V2 the currents are defined as in Fig. 8.50. 1 12 1 12 1 2
V1 V2 12
V1 2
V1 V2 R3
V1 R1
Applying Kirchhoff’s current law: 0 I3 I2 2 A
and 2 A 0 2 A 0
Expanding and rearranging: V2 V1 2 A
resulting in two equations and two unknowns (numbered for later reference): V1 V2 4 A V2 V1 2 A (8.3)
producing
V1 V2 47 V1 V2 48
V1 V2 2 1V1 3V2 24
48 1 24 3 and V1 –––––––––– 6 V 7 1 1 03 7 48 1 24 V2 –––––––––– 6 V 20 120 20 120 20
3 12
1 12
1 12
7 12
1 12
1 6
1 12
1 12
1 12
1 2
1 12
1 6
1 12
V2 6
V2 V1 12
V2 R2
V2 V1 R3
    
    
284  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Since V1 is greater than V2, the current through R3 passes from V1 to V2. Its value is
IR3 1 A
The fact that V1 is positive results in a current IR1 from V1 to ground equal to
IR1 3 A
Finally, since V2 is negative, the current IR2 flows from ground to V2 and is equal to
IR2 1 A
Supernode
On occasion there will be independent voltage sources in the network to which nodal analysis is to be applied. In such cases we can convert the voltage source to a current source (if a series resistor is present) and proceed as before, or we can introduce the concept of a supernode and proceed as follows. Start as before and assign a nodal voltage to each independent node of the network, including each independent voltage source as if it were a resistor or current source. Then mentally replace the independent voltage sources with short-circuit equivalents, and apply Kirchhoff’s current law to the defined nodes of the network.Any node including the effect of elements tied only to other nodes is referred to as a supernode (since it has an additional number of terms). Finally, relate the defined nodes to the independent voltage sources of the network, and solve for the nodal voltages. The next example will clarify the definition of supernode.
EXAMPLE 8.22 Determine the nodal voltages V1 and V2 of Fig. 8.51 using the concept of a supernode.
6V 6
V2 R2
VR2 R2
6V 2
V1 R1
VR1 R1
12 V 12
6V ( 6 V) 12
V1 V2 R3
NA
R1 4
R3
10 E
12 V
R2 2 6 A 4 A
V2V 1
FIG. 8.51 Example 8.22.
Solution: Replacing the independent voltage source of 12 V with a short-circuit equivalent will result in the network of Fig. 8.52. Even though the mental application of a short-circuit equivalent is discussed above, it would be wise in the early stage of development to redraw the
NODAL ANALYSIS (GENERAL APPROACH)  285
NA
R1 4
R3
10
R2 2 6 A 4 A
V2V 1
I1 I2
I3 I3
Supernode
FIG. 8.52 Defining the supernode for the network of Fig. 8.51.
network as shown in Fig. 8.52. The result is a single supernode for which Kirchhoff’scurrentlawmustbeapplied.Besuretoleavetheotherdefined nodes in place and use them to define the currents from that region of the network. In particular, note that the current I3 will leave the supernode at V1 and then enter the same supernode at V2.Itmust therefore appear twice when applying Kirchhoff’s current law, as shown below:
Σ Ii Σ Io 6 A I3 I1 I2 4 A I3 or I1 I2 6 A 4 A 2 A
Then 2 A
and 2 A
Relating the defined nodal voltages to the independent voltage source, we have V1 V2 E 12 V
which results in two equations and two unknowns: 0.25V1 0.5V2 2 V1 1V2 12
Substituting:
V1 V2 12 0.25(V2 12) 0.5V2 2 and 0.75V2 2 3 1
so that V2 1.333 V
and V1 V2 12 V 1.333 V 12 V 10.667 V
The current of the network can then be determined as follows:
I1 2.667 A
I2 0.667 A
I3 1.2 A 12 V 10 10.667 V ( 1.333 V) 10 V1 V2 10
1.333 V 2
V2 R2
10.667 V 4
V R1
1 0.75
V2 2
V1 4
V2 R2
V1 R1
NA286  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
A careful examination of the network at the beginning of the analysis would have revealed that the voltage across the resistor R3 must be 12 V and I3 must be equal to 1.2 A.
8.10 NODAL ANALYSIS (FORMAT APPROACH)
A close examination of Eq. (8.3) appearing in Example 8.21 reveals that the subscripted voltage at the node in which Kirchhoff’s current law is applied is multiplied by the sum of the conductances attached to that node. Note also that the other nodal voltages within the same equation are multiplied by the negative of the conductance between the two nodes. The current sources are represented to the right of the equals sign with a positive sign if they supply current to the node and with a negative sign if they draw current from the node. These conclusions can be expanded to include networks with any number of nodes. This will allow us to write nodal equations rapidly and in a form that is convenient for the use of determinants. A major requirement, however, is that all voltage sources must first be converted to current sources before the procedure is applied. Note the parallelism between the following four steps of application and those required for mesh analysis in Section 8.8:
1. Choose a reference node and assign a subscripted voltage label to the (N 1) remaining nodes of the network. 2. The number of equations required for a complete solution is equal to the number of subscripted voltages (N 1). Column 1 of each equation is formed by summing the conductances tied to the node of interest and multiplying the result by that subscripted nodal voltage. 3. We must now consider the mutual terms that, as noted in the preceding example, are always subtracted from the first column. It is possible to have more than one mutual term if the nodal voltage of current interest has an element in common with more than one other nodal voltage. This will be demonstrated in an example to follow. Each mutual term is the product of the mutual conductance and the other nodal voltage tied to that conductance. 4. The column to the right of the equality sign is the algebraic sum of the current sources tied to the node of interest. A current source is assigned a positive sign if it supplies current to a node and a negative sign if it draws current from the node. 5. Solve the resulting simultaneous equations for the desired voltages.
Let us now consider a few examples.
NODAL ANALYSIS (FORMAT APPROACH)  287
Steps 2 to 4:
and V1 V2 2
V1 V2 3 7 12 1 3
1 3
1 2
V2: V2 V1 1 4 1 3 1 3 3 A
Supplying current to node 2
Sum of conductances connected to node 2
Mutual conductance
V1: V1 V2 1 6 1 3 1 3 2 A
Drawing current from node 1
Sum of conductances connected to node 1
Mutual conductance
NA
2 A 6 R1 R2 4
R3
3 A
3
I2I 1
FIG. 8.53 Example 8.23.
Reference
R1 6
R3
3
I2 3 A R2 4 I 1 2 A
V1 V2
FIG. 8.54 Defining the nodes for the network of Fig. 8.53.
EXAMPLE 8.23 Write the nodal equations for the network of Fig. 8.53.
Solution:
Step 1: The figure is redrawn with assigned subscripted voltages in Fig. 8.54.
288  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
EXAMPLE 8.24 Find the voltage across the 3- resistor of Fig. 8.55 by nodal analysis.
NA
2
V3 8 V
–
+
6 10
4 3 1 V
–
+
–
+
FIG. 8.55 Example 8.24.
FIG. 8.56 Defining the nodes for the network of Fig. 8.55.
V3 2
V1
4 A
–
+ 4 3
10
0.1 A
V2
Reference
6
V1 V2 4 A 1 6 1 6 1 4 1 2
      
V2 V1 0.1 A
V1 V2 4
V1 V2 0.1
resulting in
11V1 2V2 48 5V1 18V2 3
and
11 48 5 3 33 240 207 V2 V3 ––––––––– –––––––––– –––– 1.101 V 11 2 198 10 188 5 18
As demonstrated for mesh analysis, nodal analysis can also be a very useful technique for solving networks with only one source.
3 5
1 6
1 6
11 12
1 6
1 6
1 3
1 10
Solution: Converting sources and choosing nodes (Fig. 8.56), we have
NODAL ANALYSIS (FORMAT APPROACH)  289
EXAMPLE 8.25 Using nodal analysis, determine the potential across the 4- resistor in Fig. 8.57.
Solution 1: The reference and four subscripted voltage levels were chosen as shown in Fig. 8.58. A moment of reflection should reveal that for any difference in potential between V1 and V3, the current through and the potential drop across each 5- resistor will be the same. Therefore, V4 is simply a midvoltage level between V1 and V3 and is known if V1 and V3 are available. We will therefore not include it in a nodal voltage and will redraw the network as shown in Fig. 8.59. Understand, however, that V4 can be included if desired, although four nodal voltages will result rather than the three to be obtained in the solution of this problem. V1: V1 V2 V3 0 1 10 1 2 1 10 1 2 1 2
NA
2
3 A
2
4 2
5 5
FIG. 8.57 Example 8.25.
2
3 A
2
4 2
5 5
V1
V4
V3V 2
(0 V)
FIG. 8.58 Defining the nodes for the network of Fig. 8.57.
2
3 A
2
4 2
V1
10
(0 V)
V2 V3
FIG. 8.59 Reducing the number of nodes for the network of Fig. 8.57 by combining the two 5- resistors.
V2: V2 V1 V3 3 A 1 2 1 2 1 2 1 2 V3: V3 V2 V1 0
which are rewritten as
1.1V1 0.5V2 0.1V3 0 V2 0.5V1 0.5V3 3 0.85V3 0.5V2 0.1V1 0
For determinants,
Before continuing, note the symmetry about the major diagonal in the equation above. Recall a similar result for mesh analysis. Examples 8.23 and 8.24 also exhibit this property in the resulting equations. Keep this thought in mind as a check on future applications of nodal analysis.
1.1 0.5 0 0.5 13 0.1 0.5 0 V3 V4 ––––––––––––––––––– 4.645 V 1.1 0.5 0.1 0.5 1 0.5 0.1 0.5 0.85
Mathcad Solution: By now the sequence of steps necessary to solve a series of equations using Mathcad should be quite familiar and less threatening than the first encounter. For this example, all the parameters were entered in the three simultaneous equations, avoiding the
1.1V1 0.5V2 0.1V3 0
0.1V1 0.5V2 0.85V3 0
0.5V1 1V2 0.5V3 3
cba
b
a
1 10
1 2
1 4
1 2
1 10
290  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
need to define each parameter of the network. Simply provide a Guess at the three nodal voltages, apply the word Given, and enter the three equations properly as shown in Fig. 8.60. It does take some practice to ensure that the bracket is moved to the proper location before making an entry, but this is simply part of the rules set up to maintain control of the operations to be performed. Finally, request the desired nodal voltages using the correct format. The numerical results will appear, again confirming our theoretical solutions.
NA
3 4 1
9
240 V 6 6 2 – +
FIG. 8.61 Example 8.26.
FIG. 8.60 Using Mathcad to verify the mathematical calculations of Example 8.25.
The next example has only one source applied to a ladder network.
EXAMPLE 8.26 Write the nodal equations and find the voltage across the 2- resistor for the network of Fig. 8.61.
BRIDGE NETWORKS  291
V1: V1 V2 0 20 V 1 4 1 4 1 6 1 12
NA
FIG. 8.62 Converting the voltage source to a current source and defining the nodes for the network of Fig. 8.61.
12
V1
2 20 A 6 6
(0 V)
1 4
V2 V3
Solution: The nodal voltages are chosen as shown in Fig. 8.62.
V2: V2 V1 V3 0 1 1 1 4 1 1 1 6 1 4 V3: V3 V2 0 0
and
0.5V1 0.25V2 0 20
0.25V1 V2 1V3 0
0 1V2 1.5V3 0
Note the symmetry present about the major axis. Application of determinants reveals that
V3 V2 10.667 V
8.11 BRIDGE NETWORKS
This section introduces the bridge network, a configuration that has a multitude of applications. In the chapters to follow, it will be employed in both dc and ac meters. In the electronics courses it will be encountered early in the discussion of rectifying circuits employed in converting a varying signal to one of a steady nature (such as dc). A number of other areas of application also require some knowledge of ac networks; these areas will be discussed later. The bridge network may appear in one of the three forms as indicated in Fig. 8.63. The network of Fig. 8.63(c) is also called a symmetrical lattice network if R2 R3 and R1 R4. Figure 8.63(c) is an excellent example of how a planar network can be made to appear nonplanar. For the purposes of investigation, let us examine the network of Fig. 8.64 using mesh and nodal analysis.
17 12
1 1
1 2
1 1
292  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Mesh analysis (Fig. 8.65) yields
(3 4 2 )I1 (4 )I2 (2 )I3 20 V (4 5 2 )I2 (4 )I1 (5 )I3 0 (2 5 1 )I3 (2 )I1 (5 )I2 0
and 009I1 4I2 2I3 20 4I1 11I2 5I3 0 2I1 5I2 8I3 0
with the result that
I1 4 A I2 2.667 A I3 2.667 A
The net current through the 5- resistor is
I5 I2 I3 2.667 A 2.667 A 0 A
Nodal analysis (Fig. 8.66) yields V1 V2 V3 A 20 3 1 2 1 4 1 2 1 4 1 3
NA
(b)
R2R 1
R3 R4
R5
R1 R2 R5
R3 R4
(a) (c)
R2
R1
R3
R4
R5
FIG. 8.63 Various formats for a bridge network.
FIG. 8.64 Standard bridge configuration.
Rs 3 R2
2
R3
2
5
R5
1
R4
4
R1
E 20 V
Rs 3 R2 2
R3
1
R1
E 20 V
I1
4 R5 I2 I35 2 R4
FIG. 8.65 Assigning the mesh currents to the network of Fig. 8.64.
R1
R2R 5
R3
R4
2
3 IR s V2
V1
V3
4
5 2
1
20 3 A
(0 V)
FIG. 8.66 Defining the nodal voltages for the network of Fig. 8.64.
det[[20/3, 1/4, 1/2][0,(1/4 1/2 1/5), 1/5][0, 1/5,(1/5 1/2 1/1)]] ENTER 10.5
CALC. 8.4
V2 V1 V3 0 1 5 1 4 1 5 1 2 1 4 V3 V1 V2 0
and
V1 V2 V3 A 20 3 1 2 1 4 1 2 1 4 1 3
1 5
1 2
1 1
1 2
1 5
V1 V2 V3 0 1 5 1 5 1 2 1 4 1 4 V1 V2 V3 0
Note the symmetry of the solution. WiththeTI-86calculator,thetoppartofthedeterminantisdetermined by the following (take note of the calculations within parentheses):
1 1
1 2
1 5
1 5
1 2
BRIDGE NETWORKS  293
NA
with the bottom of the determinant determined by:
det[[(1/3 1/4 1/2), 1/4, 1/2][ 1/4,(1/4 1/2 1/5), 1/5][ 1/2, 1/5,(1/5 1/2 1/1)]] ENTER 1.312
CALC. 8.5
Finally,
10.5/1.312 ENTER 8
CALC. 8.6
and V1 8 V
Similarly, V2 2.667 V and V3 2.667 V
and the voltage across the 5- resistor is
V5 V2 V3 2.667 V 2.667 V 0 V
Since V5 0V,wecan insert a short in place of the bridge arm without affecting the network behavior. (Certainly V IR I·(0) 0V.) In Fig. 8.67, a short circuit has replaced the resistor R5, and the voltageacrossR4 istobedetermined.ThenetworkisredrawninFig.8.68,and
V1 (voltage divider rule)
 
2.667 V
as obtained earlier. We found through mesh analysis that I5 0A ,which has as its equivalent an open circuit as shown in Fig. 8.69(a). (Certainly I V/R 0/(∞ ) 0A.) The voltage across the resistor R4 will again be determined and compared with the result above. The network is redrawn after combining series elements, as shown in Fig. 8.69(b), and
V3 8 V
and V1 2.667 V
as above. The condition V5 0 V or I5 0 A exists only for a particular relationship between the resistors of the network. Let us now derive this relationship using the network of Fig. 8.70, in which it is indicated that I 0 A and V 0 V. Note that resistor Rs of the network of Fig. 8.69 will not appear in the following analysis. The bridge network is said to be balanced when the condition of I 0 A orV 0Vexists. If V 0 V (short circuit between a and b), then
V1 V2
8 V 3
1 (8 V) 1 2
2 (20 V) 2 3
(6 3 )(20 V) 6 3 3
40 V 15
2(20 V) 2 4 9
2 3 (20 V) 2 3 4 3 9 3
2 3 (20 V) 2 3 8 6 3
(2 1 )20 V (2 1 ) (4 2 ) 3
R1
R2
R3
R4
2
E
4
2
1
V  =  0
Rs 3
20 V
–
+ V1
FIG. 8.67 Substituting the short-circuit equivalent for the balance arm of a balanced bridge.
R1 2
–
+
4 R2
R3 1 2 R4
Rs 3
E 20 V V1 – +
FIG. 8.68 Redrawing the network of Fig. 8.67.
294  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
and I1R1 I2 R2
or I1
In addition, when V 0 V,
V3 V4 and I3 R3 I4 R4 If we set I 0 A, then I3 I1 and I4 I2, with the result that the above equation becomes
I1R3 I2 R4
Substituting for I1 from above yields R3 I2 R4
or, rearranging, we have
(8.4)
This conclusion states that if the ratio of R1 to R3 is equal to that of R2 to R4, the bridge will be balanced, and I 0 A or V 0 V. A method of memorizing this form is indicated in Fig. 8.71. For the example above, R1 4 , R2 2 , R3 2 , R4 1 , and
2
The emphasis in this section has been on the balanced situation. Understand that if the ratio is not satisfied, there will be a potential drop across the balance arm and a current through it. The methods just described (mesh and nodal analysis) will yield any and all potentials or currents desired, just as they did for the balanced situation.
8.12 Y-D (T-p) AND D-Y (p-T) CONVERSIONS
Circuit configurations are often encountered in which the resistors do not appear to be in series or parallel. Under these conditions, it may be necessary to convert the circuit from one form to another to solve for
2 1
4 2
R2 R4
R1 R3
R R 1 3 R R 2 4
I2 R2 R1
I2 R2 R1
NA
R1
R2
R3
R4
2
E
4
2
1
Rs 3
20 V
–
+
–
+
I  =  0
(a)
V1
6
3 R s
3
E 20 V – +
(b)
FIG. 8.69 Substituting the open-circuit equivalent for the balance arm of a balanced bridge.
R1
R3E
V  =  0
Rs
–
+
I  =  0
R4
V4
I4
I1V 1– + I2
V2
–
+ R2
V3
–
+ I3
–+
FIG. 8.70 Establishing the balance criteria for a bridge network.
R1
R3
R2
R4
R1 R3
R2 R4
=
FIG. 8.71 A visual approach to remembering the balance condition.
NA
Y-D (T-p) AND D-Y (p-T) CONVERSIONS  295
any unknown quantities if mesh or nodal analysis is not applied. Two circuit configurations that often account for these difficulties are the wye (Y) and delta ( ) configurations, depicted in Fig. 8.72(a). They are also referred to as the tee (T) and pi ( ), respectively, as indicated in Fig. 8.72(b). Note that the pi is actually an inverted delta.
RB
RC
RA
“ ”
R1 R2
R3
“”
RB RA
RC
“”
(a) (b)
R1 R2
R3
“”
FIG. 8.72 The Y (T) and D (p) configurations.
The purpose of this section is to develop the equations for converting from D to Y, or vice versa. This type of conversion will normally lead to a network that can be solved using techniques such as those described in Chapter 7. In other words, in Fig. 8.73, with terminals a, b, and c held fast, if the wye (Y) configuration were desired instead of the inverted delta (D) configuration, all that would be necessary is a direct application of the equations to be derived. The phrase instead of is emphasized to ensure that it is understood that only one of these configurations is to appear at one time between the indicated terminals. It is our purpose (referring to Fig. 8.73) to find some expression for R1, R2, and R3 in terms of RA, RB, and RC, and vice versa, that will ensure that the resistance between any two terminals of the Y configuration will be the same with the D configuration inserted in place of the Y configuration (and vice versa). If the two circuits are to be equivalent, the total resistance between any two terminals must be the same. Consider terminals a-c in the D-Y configurations of Fig. 8.74.
a
RAR B R3
R2R 1
RC
b
c
“ ”
FIG. 8.73 Introducing the concept of D-Y or Y-D conversions.
R1 R2
R3
a b
c
Ra-c RB RA
RC
a b
c
Ra-c
RB RA
RC
a
b
c
Ra-c
External to path of measurement
FIG. 8.74 Finding the resistance Ra-c for the Y and D configurations.
296  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Let us first assume that we want to convert the D (RA,R B,RC) to theY (R1, R2, R3). This requires that we have a relationship for R1, R2, and R3 in terms of RA,RB, and RC.Ifthe resistance is to be the same between terminals a-c for both the D and theY, the following must be true:
Ra-c (Y) Ra-c (D)
so that (8.5a)
Using the same approach for a-b and b-c, we obtain the following relationships:
(8.5b)
and (8.5c)
Subtracting Eq. (8.5a) from Eq. (8.5b), we have (R1 R2) (R1 R3)
so that (8.5d)
Subtracting Eq. (8.5d) from Eq. (8.5c) yields (R2 R3) (R2 R3)
so that 2R3 RA 2R R B B R A
RC resulting in the following expression for R3 in terms of RA, RB, and RC:
(8.6a)
Following the same procedure for R1 and R2, we have
(8.6b)
and (8.6c)
Note that each resistor of the Y is equal to the product of the resistors in the two closest branches of the D divided by the sum of the resistors in the D.
R2 RA R R A R B C RC
R1 RA R R B R B C RC
R3 RA R R A B RB RC
RA RC RB RA RA RB RC
RA RB RA RC RA RB RC
R2 R3 R R A A R C R B
R B R R A C
RB RA RB RC RA RB RC
RC RB RC RA RA RB RC
Rb-c R2 R3 RA RA (R ( B RB RC R ) C)
Ra-b R1 R2 RC RC (R ( A RA RB R ) B)
Ra-c R1 R3 RB R B(R ( A RA RC R ) C)
NA
Y-D (T-p) AND D-Y (p-T) CONVERSIONS  297
To obtain the relationships necessary to convert from a Y to a D, first divide Eq. (8.6a) by Eq. (8.6b):
R R C A
or RA
Then divide Eq. (8.6a) by Eq. (8.6c):
R R C B
or RB
Substituting for RA and RB in Eq. (8.6c) yields
R2

Placing these over a common denominator, we obtain
R2

and RC (8.7a)
We follow the same procedure for RB and RA:
RA (8.7b)
and RB (8.7c)
Note that the value of each resistor of the D is equal to the sum of the possible product combinations of the resistances of the Y divided by the resistance of the Y farthest from the resistor to be determined.
Let us consider what would occur if all the values of a D or Y were the same. If RA RB RC, Equation (8.6a) would become (using RA only) the following:
R3 RA R R AR B B RC RA R R AR A A RA 3 R R 2 A A
and, following the same procedure,
R1 R2
RA 3
RA 3
RA 3
R1R2 R1R3 R2R3 R2
R1R2 R1R3 R2R3 R1
R1R2 R1R3 R2R3 R3
R2R3RC R1R2 R1R3 R2R3
(R3RC /R1) (R1R2 R1R3 R2R3)/(R1R2)
(R3 /R1)RC (R3 /R2) (R3 /R1) 1
(RC R3 /R1)RC (R3 RC /R2) (RC R3/R1) RC
R3 RC R2
(RARB)/(RA RB RC) (RARC)/(RA RB RC)
R3 R2
RC R3 R1
(RA RB)/(RA RB RC) (RB RC)/(RA RB RC)
R3 R1
NA
298  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
In general, therefore,
(8.8a)
or (8.8b)
which indicates that for a Y of three equal resistors, the value of each resistor of the D is equal to three times the value of any resistor of the Y. If only two elements of a Y or a D are the same, the corresponding D or Y of each will also have two equal elements. The converting of equations will be left as an exercise for the reader. The Y and the D will often appear as shown in Fig. 8.75. They are then referred to as a tee (T) and a pi ( ) network, respectively. The equations used to convert from one form to the other are exactly the same as those developed for the Y and D transformation.
RD 3RY
RY R 3 D
NA
(a)
R1
1
2
3
4
R2
R3
“”“” “ ”
RC
1
2
3
4
RB RA
“ ”
(b)
FIG. 8.75 The relationship between the Y and T configurations and the D and p configurations.
EXAMPLE 8.27 Convert the D of Fig. 8.76 to a Y.
RB
RA
RCa
b
c
a
b
c
20
30
10
FIG. 8.76 Example 8.27.
R3 10
R1
31/3 R2
5
a ba b
c
c
FIG. 8.77 The Y equivalent for the D of Fig. 8.76.
Solution:
R1 3
R2 5
R3 10
The equivalent network is shown in Fig. 8.77 (page 298).
EXAMPLE 8.28 Convert the Y of Fig. 8.78 to a D.
Solution:
RA


RA 180
However, the three resistors for the Y are equal, permitting the use of Eq. (8.8) and yielding
RD 3RY 3(60 ) 180 and RB RC 180
The equivalent network is shown in Fig. 8.79.
EXAMPLE 8.29 Find the total resistance of the network of Fig. 8.80, where RA 3 , RB 3 , and RC 6 .
Solution:
Two resistors of the D were equal; therefore, two resistors of the Y will be equal.
R1 1.5
R2 1.5
R3 0.75
Replacing the D by the Y, as shown in Fig. 8.81, yields
RT 0.75
0.75
0.75 2.139 RT 2.889
(5.5 )(3.5 ) 5.5 3.5
(4 1.5 )(2 1.5 ) (4 1.5 ) (2 1.5 )
9 12
(3 )(3 ) 12
RARB RA RB RC
18 12
(3 )(6 ) 12
RARC RA RB RC
18 12
(3 )(6 ) 3 3 6
RBRC RA RB RC
10,800 60
3600 3600 3600 60
(60 )(60 ) (60 )(60 ) (60 )(60 ) 60
R1R2 R1R3 R2R3 R1
600 60
(20 )(30 ) 60
RARB RA RB RC
300 60
(30 )(10 ) 60
RARC RA RB RC
1 3
200 60
(20 )(10 ) 30 20 10
RB RC RA RB RC
←−
Y-D (T-p) AND D-Y (p-T) CONVERSIONS  299
NA
R3 60
R1
60 R2
60
a ba
b
c
c
FIG. 8.78 Example 8.28.
RC
RB
180 RA
a ba
b
c
c
180
180
FIG. 8.79 The D equivalent for the Y of Fig. 8.78.
RB
3
RA
3
ba
c
4 2
6 “    ”R T RC
FIG. 8.80 Example 8.29.
RT
0.75
R1
ba
c
4 2
1.5 1.5
R3
R2
FIG. 8.81 Substituting the Y equivalent for the bottom D of Fig. 8.80.
←
300  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
EXAMPLE 8.30 Find the total resistance of the network of Fig. 8.82.
Solutions: Since all the resistors of the D or Y are the same, Equations (8.8a) and (8.8b) can be used to convert either form to the other. a. Converting the D to a Y. Note: When this is done, the resulting d′ of the new Y will be the same as the point d shown in the original figure, only because both systems are “balanced.” That is, the resistance in each branch of each system has the same value:
RY 2 (Fig. 8.83) 6 3 RD 3
NA
FIG. 8.82 Example 8.30.
RT
6
a
bc
9
6
9 9
6
d
d*
2
2 2
a
bc
6
a
bc
6
6
FIG. 8.83 Converting the D configuration of Fig. 8.82 to a Y configuration.
RT
9
a
2
d, d
cb
9 9
2 2
FIG. 8.84 Substituting the Y configuration for the converted D into the network of Fig. 8.82.
RT
6
a
bc
27
6
6
27 27
FIG. 8.85 Substituting the converted Y configuration into the network of Fig. 8.82.
The network then appears as shown in Fig. 8.84. RT 2 3.2727
b. Converting the Y to a D:
RD 3RY (3)(9 ) 27 (Fig. 8.85)
R′T 4.9091
RT
3.2727
which checks with the previous solution.
2(4.9091 ) 3
2R′T 3
R′T2R′T 3R′T
R′T (R′T R′T) R′T (R′T R′T)
162 33
(6 )(27 ) 6 27
(2 )(9 ) 2 9
APPLICATIONS  301
NA
8.13 APPLICATIONS
The Applications section of this chapter will discuss the constant current characteristic in the design of security systems, the bridge circuit in a common residential smoke detector, and the nodal voltages of a digital logic probe.
Constant Current Alarm Systems
The basic components of an alarm system employing a constant current supply are provided in Fig. 8.86. This design is improved over that provided in Chapter 5 in the sense that it is less sensitive to changes in resistance in the circuit due to heating, humidity, changes in the length of the line to the sensors, and so on. The 1.5-k rheostat (total resistance between points a and b) is adjusted to ensure a current of 5 mA through the single-series security circuit. The adjustable rheostat is necessary to compensate for variations in the total resistance of the circuit introduced by the resistance of the wire, sensors, sensing relay, and milliammeter. The milliammeter is included to set the rheostat and ensure a current of 5 mA.
Magnetic switch
Window foil
Door switch
Sensing relay
1 kΩ
≅ 5 mA
E 10 V + –
Rheostat 0     1.5 kΩ
10-mA movement
N/C
N/O 5 V @ 5 mA
To bell circuit
1 kΩ
a
b
FIG. 8.86 Constant current alarm system.
If any of the sensors should open, the current through the entire circuit will drop to zero, the coil of the relay will release the plunger, and contact will be made with the N/C position of the relay. This action will complete the circuit for the bell circuit, and the alarm will sound. For the future, keep in mind that switch positions for a relay are always shown with no power to the network, resulting in the N/C position of Fig. 8.86. When power is applied, the switch will have the position indicated by the dashed line. That is, various factors, such as a change in resistance of any of the elements due to heating, humidity, and so on, would cause the applied voltage to redistribute itself and create a sensitive situation. With an adjusted 5 mA, the loading can change, but the current will always be 5 mA and the chance of tripping reduced. Take note of the fact that the relay is rated as 5 V at 5 mA, indicating that in the on state the voltage across the relay is 5 V and the current through the relay 5 mA. Its internal resistance is therefore 5 V/5 mA 1 k in this state. A more advanced alarm system using a constant current is provided in Fig. 8.87. In this case an electronic system employing a single tran
302  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
sistor, biasing resistors, and a dc battery are establishing a current of 4 mA through the series sensor circuit connected to the positive side of an operational amplifier (op-amp). Although the transistor and op-amp devices may be new to you, they will be discussed in detail in your electronics courses—you do not need to be aware of the details of their operation for now. Suffice it to say for the moment that the transistor in this application is being used not as an amplifier but as part of a design to establish a constant current through the circuit. The op-amp is a very useful component of numerous electronic systems, and it has important terminal characteristics established by a variety of components internal to its design. The LM2900 operational amplifier of Fig. 8.87 is one of four found in the dual-in-line integrated circuit package appearing in Fig. 8.88(a). Pins 2, 3, 4, 7, and 14 were used for the design of Fig. 8.87. Note in Fig. 8.88(b) the number of elements required to establish the desired terminal characteristics—the details of which will be investigated in your electronics courses. In Fig. 8.87, the designed 15-V dc supply, biasing resistors, and transistor in the upper right-hand corner of the schematic establish a constant 4-mA current through the circuit. It is referred to as a constant current source because the current will remain fairly constant at 4 mA even though there may be moderate variations in the total resistance of the series sensor circuit connected to the transistor. Following the 4 mA through the circuit, we find that it enters terminal 2 (positive side of the input) of the op-amp. A second current of 2 mA, called the reference current, is established by the 15-V source and resistance R and enters terminal 3 (negative side of the input) of the op-amp. The reference current of 2 mA is necessary to establish a current for the 4-mA current of the network to be compared against. So long as the 4-mA current exists, the operational amplifier will provide a “high” output voltage that exceeds 13.5 V, with a typical level of 14.2 V (according to the specification sheet for the op-amp). However, if the sensor current drops from 4 mA to a level below the reference level of 2 mA, the op-amp will respond with a “low” output voltage that is typically about 0.1 V. The output of the operational amplifier will then signal the alarm circuit about the disturbance. Note from the above that it is not necessary for the sensor current to drop to 0 mA to signal the alarm circuit—just a variation around the reference level that appears unusual. One very important characteristic of this particular op-amp is that the input impedance to the op-amp is relatively low. This feature is important because you don’t want alarm circuits reacting to every voltage spike or turbulence that comes down the line because of external switching action
NA
Magnetic switch
Window foil
Door switch
2 mA
4 mA
+15 V
Rref
3
2
+15 V
+
–
LM2900
14
7
4
Output
Constant current source
To alarm bell circuit
+15 V
4 mA
RE
R2
R1
Op-Amp
FIG. 8.87 Constant current alarm system with electronic components.
(a)
V+
14
200 µA
4
Output
–Input
+Input
3
2
7
(b)
+ Vhigh –
+
–
RseriesV
+
–
0
Vlow
Rlow Op-Amp
(c)
7
INPUT 3+
On package to identify pin numbers
Dual-in-line package
V+ INPUT 4+ INPUT 4– OUTPUT 4 OUTPUT 3 INPUT 3–
14 13 12 11 10 9 8
4
–
+
2
–
+
–
+
–
+
3
1
1 2 3 4 5 6 7 INPUT 1+ INPUT 2+ INPUT 2– OUTPUT 2 GND OUTPUT 1 INPUT 1–
TOP VIEW
FIG. 8.88 LM2900 operational amplifier: (a) dual-inline package (DIP); (b) components; (c) impact of low-input impedance.
APPLICATIONS  303
or outside forces such as lightning. In Fig. 8.88(c), for instance, if a high voltage should appear at the input to the series configuration, most of the voltage will be absorbed by the series resistance of the sensor circuit rather than traveling across the input terminals of the operational amplifier—thus preventing a false output and an activation of the alarm.
Wheatstone Bridge Smoke Detector
TheWheatstonebridgeisapopularnetworkconfigurationwheneverdetectionofsmallchangesinaquantityisrequired.InFig.8.89(a),thedcbridge configurationisemployingaphotoelectricdevicetodetectthepresenceof smoke and to sound the alarm. A photograph of an actual photoelectric smokedetectorappearsinFig.8.89(b),andtheinternalconstructionofthe unitisshowninFig.8.89(c).Firstnotethatairventsareprovidedtopermit thesmoketoenterthechamberbelowtheclearplastic.Theclearplasticwill preventthesmokefromenteringtheupperchamberbutwillpermitthelight
NA
(a)
Balance adjust
Rbalance
Reference
Sensitive relay
Vbalance +–
Smoke detector
R
Lamp
N/C
N/O
To alarm circuit
+
–
DC power
ab

















FIG. 8.89(a)(b) Wheatstone bridge detector: (a) dc bridge configuration; (b) outside appearance.
304
from the bulb in the upper chamber to bounce off the lower reflector to the semiconductor light sensor (a cadmium photocell) at the left side of the chamber.Theclearplasticseparationensuresthatthelighthittingthelight sensorintheupperchamberisnotaffectedbytheenteringsmoke.Itestablishes a reference level to compare against the chamber with the entering smoke.Ifnosmokeispresent,thedifferenceinresponsebetweenthesensor cells will be registered as the normal situation. Of course, if both cells wereexactlyidentical,andiftheclearplasticdidnotcutdownonthelight, bothsensorswouldestablishthesamereferencelevel,andtheirdifference wouldbezero.However,thisisseldomthecase,soareferencedifferenceis recognized as the sign that smoke is not present. However, once smoke is present, there will be a sharp difference in the sensor reaction from the norm,andthealarmshouldbesounded. In Fig. 8.89(a), we find that the two sensors are located on opposite armsofthebridge.Withnosmokepresentthebalance-adjustrheostatwill beusedtoensurethatthevoltageVbetweenpointsaandbiszerovoltsand theresultingcurrentthroughtheprimaryofthesensitiverelaywillbezero amperes. Taking a look at the relay, we find that the absence of a voltage from a to b will leave the relay coil unenergized and the switch in the N/O position (recall that the position of a relay switch is always drawn in the unenergized state).An unbalanced situation will result in a voltage across the coil and activation of the relay, and the switch will move to the N/C position to complete the alarm circuit and activate the alarm. Relays with two contacts and one movable arm are called single-pole–double-throw (SPDT) relays. The dc power is required to set up the balance situation, energizetheparallelbulbsoweknowthatthesystemison,andprovidethe voltage from a to b if an unbalanced situation should develop. One may ask why only one sensor isn’t used since its resistance would be sensitive to the presence of smoke. The answer lies in the fact that the smoke detector might generate a false readout if the supply voltage or output light intensity of the bulb should vary. Smoke detectors of the type just described must be used in gas stations, kitchens, dentist offices, etc., where the range of gas fumes present may set off an ionizing type smoke detector.
Ceiling Reflector
Reference cell
Sealed chamber
Solid barrier
Light source
Clear plastic
Reflector
Vents for the passage of air or smoke
Room
Smoke detector
Photoconductive cells (Resistance a function of applied light)
(c)
FIG. 8.89(c) Wheatstone bridge smoke detector: (c) internal construction.
APPLICATIONS  305
Schematic with Nodal Voltages
When an investigator is presented with a system that is down or not operating properly, one of the first options is to check the system’s specified voltages on the schematic. These specified voltage levels are actually the nodal voltages determined in this chapter. Nodal voltage is simply a special term for a voltage measured from that point to ground. The technician will attach the negative or lower-potential lead to the ground of the network (often the chassis) and then place the positive or higher-potential lead on the specified points of the network to check the nodal voltages. If they match, it is a good sign that that section of the system is operating properly. If one or more fail to match the given values, the problem area can usually be identified. Be aware that a reading of 15.87 V is significantly different from an expected reading of 16 V if the leads have been properly attached. Although the actual numbers seem close, the difference is actually more than 30 V. One must expect some deviation from the given value as shown, but always be very sensitive to the resulting sign of the reading. The schematic of Fig. 8.90(a) includes the nodal voltages for a logic probe used to measure the input and output states of integrated circuit logic chips. In other words, the probe determines whether the measured voltage is one of two states: high or low (often referred to as “on” or “off” or 1 or 0). If the LOGIC IN terminal of the probe is placed on a chip at a location where the voltage is between 0 and 1.2 V, the voltage is considered a low level, and the green LED will light. (LEDs are lightemitting semiconductor diodes that will emit light when current is passed through them.) If the measured voltage is between 1.8 V and 5V, the reading is considered high, and the red LED will light. Any voltage between 1.2 V and 1.8 V is considered a “floating level” and is an indication that the system being measured is not operating correctly. Note that the reference levels mentioned above are established by the voltage divider network to the right of the schematic. The op-amps employed are of such high input impedance that their loading on the voltage divider network can be ignored and the voltage divider network considered a network unto itself. Even though three 5.5-V dc supply voltages are indicated on the diagram, be aware that all three points are connected to the same supply. The other voltages provided (the nodal voltages) are the voltage levels that should be present from that point to ground if the system is working properly. The op-amps are used to sense the difference between the reference at points 3 and 6 and the voltage picked up in LOGIC IN. Any difference will result in an output that will light either the green or the red LED. Be aware, because of the direct connection, that the voltage at point 3 is the same as shown by the nodal voltage to the left, or 1.8 V. Likewise, the voltage at point 6 is 1.2 V for comparison with the voltages at points 5 and 2, which reflect the measured voltage. If the input voltage happened to be 1.0 V, the difference between the voltages at points 5 and 6 would be 0.2 V, which ideally would appear at point 7. This low potential at point 7 would result in a current flowing from the much higher 5.5-V dc supply through the green LED, causing it to light and indicating a low condition. By the way, LEDs, like diodes, permit current through them only in the direction of the arrow in the symbol. Also note that the voltage at point 6 must be higher than that at point 5 for the output to turn on the LED. The same is true for point 2 over point 3, which reveals why the red LED does not light when the 1.0-V level is measured.
NA
306  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Oftentimes it is impractical to draw the full network as shown in Fig. 8.90(b) because there are space limitations or because the same voltage divider network is used to supply other parts of the system. In such cases one must recognize that points having the same shape are connected, and the number in the figure reveals how many connections are made to that point.
NA
FIG. 8.90 Logic probe: (a) schematic with nodal voltages; (b) network with global connections; (c) photograph of commercially available unit.












– +
– +
+5.5 V
R1 6.8 kΩ
1.8 V
1.5 V
1.2 V
R2 560 Ω
R3 560 Ω
R4 2.2 kΩ
R5
1 MΩ
34
2 11
4
11
7
+5.5 V
+5.5 V
U2A LM324
5
6
High
Low
R6
10 kΩ
TP LOGIC IN
LED 1 Red
LED 2 Green
+5.5 V
R7
1.2 kΩ
(b)
1
1
1
1
1
1
– +
– +
+5.5 V
R1 6.8 kΩ
1.8 V
1.5 V
1.2 V
R2 560 Ω
R3 560 Ω
R4 2.2 kΩ
R5
1 MΩ
34
2 11
4
11
7
+5.5 V
+5.5 V
U2A LM324
5
6
High
Low
R6
10 kΩ
TP LOGIC IN
LED 1 Red
LED 2 Green
+5.5 V
R7
1.2 kΩ
(a)
U2B LM324
1
1
U2B LM324
A photograph of the outside and inside of a commercially available logic probe is provided in Fig. 8.90(c). Note the increased complexity of system because of the variety of functions that the probe can perform.
8.14 COMPUTER ANALYSIS
PSpice
The bridge network of Fig. 8.70 will now be analyzed using PSpice to ensure that it is in the balanced state. The only component that has not been introduced in earlier chapters is the dc current source. It can be obtained by first selecting the Place a part key and then the SOURCE library. Scrolling the Part List will result in the option IDC. A left click of IDC followed by OK will result in a dc current source whose direction is toward the bottom of the screen. One left click of the mouse (to make it red—active) followed by a right click of the mouse will result in a listing having a Mirror Vertically option. Selecting that option will flip the source and give it the direction of Fig. 8.70. The remaining parts of the PSpice analysis are pretty straightforward, with the results of Fig. 8.91 matching those obtained in the analysis of Fig. 8.70. The voltage across the current source is 8 V positive to ground, and the voltage at either end of the bridge arm is 2.667 V. The voltage across R5 is obviously 0 V for the level of accuracy displayed, and the current is of such a small magnitude compared to the other current levels of the network that it can essentially be considered 0 A. Note also for the balanced bridge that the current through R1 equals that of R3, and the current through R2 equals that of R4.
NA COMPUTER ANALYSIS  307
FIG. 8.91 Applying PSpice to the bridge network of Fig. 8.70.
For the analysis, both indicators and a meter will be used to display the desired results. An A indicator in the H position was used for the current through R5, and a V indicator in the V position was used for the voltage across R2. A multimeter in the voltmeter mode was placed to read the voltage across R4. The ammeter is reading the mesh or loop current for that branch, and the two voltmeters are displaying the nodal voltages of the network. After simulation, the results displayed are an exact match with those of Example 8.18.
308  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
Electronics Workbench
Electronics Workbench will now be used to verify the results of Example 8.18. All the elements of creating the schematic of Fig. 8.92 have been presented in earlier chapters; they will not be repeated here in order to demonstrate how little documentation is now necessary to carry you through a fairly complex network.
NA
FIG. 8.92 Using Electronics Workbench to verify the results of Example 8.18.
NA
PROBLEMS  309
R1
E Vab I 6 A
3
a
b
+
–
10 V
FIG. 8.93 Problem 1.
Rs 10 k
2
4 AI 6 V + –
(a)
2
4 AI 6 V + –
(b)
FIG. 8.94 Problem 2.
2. a. Determine V for the current source of Fig. 8.94(a) with an internal resistance of 10 k . b. The source of part (a) is approximated by an ideal current source in Fig. 8.94(b) since the source resistance is much larger than the applied load. Determine the resulting voltage V for Fig. 8.94(b), and compare it to that obtained in part (a). Is the use of the ideal current source a good approximation?
PROBLEMS
SECTION 8.2 Current Sources 1. Find the voltage Vab (with polarity) across the ideal current source of Fig. 8.93.
3. For the network of Fig. 8.95: a. Find the currents I1 and Is. b. Find the voltages Vs and V3. 4. Find the voltage V3 and the current I2 for the network of Fig. 8.96.
FIG. 8.95 Problem 3.
R1 2
6
4 A I 2 V3 + –
R2
R3E 24 VV s + – I1 Is
FIG. 8.96 Problem 4.
R1 6
0.6 A
I
16 V3 + –
R3
I2 R2 24
8 R 4
SECTION 8.3 Source Conversions
5. Convert the voltage sources of Fig. 8.97 to current sources.
310  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
NA
E 18 V
(a)
Rs
6
E 9 V
(b)
Rs
2.2 k
FIG. 8.97 Problem 5.
6. Convert the current sources of Fig. 8.98 to voltage sources.
Rs3
1.5 A
(a)
Rs
4.7 k
6 mA
(b)
II
FIG. 8.98 Problem 6.
FIG. 8.99 Problem 7.
Rs 4 12 A I RL 2
FIG. 8.100 Problem 8.
R1
10
R2
6.8
R3 39 E 12 V
I1
Vab
a
b
I  =  2 A
7. For the network of Fig. 8.99: a. Find the current through the 2- resistor. b. Convert the current source and 4- resistor to a voltage source, and again solve for the current in the 2- resistor. Compare the results.
8. For the configuration of Fig. 8.100: a. Convert the current source and 6.8- resistor to a voltage source. b. Find the magnitude and direction of the current I1. c. Find the voltage Vab and the polarity of points a and b.
PROBLEMS  311
NA
SECTION 8.4 Current Sources in Parallel 9. Find the voltage V2 and the current I1 for the network of Fig. 8.101.
10. a. Convert the voltage sources of Fig. 8.102 to current sources. b. Find the voltage Vab and the polarity of points a and b. c. Find the magnitude and direction of the current I.
FIG. 8.101 Problem 9.
7 A
I1
V2R 1 4 R2 6 3 A + –
FIG. 8.102 Problem 10.
R1 3
E1 9 V
R2 2
E2 20 V
R3 6 R4 12
I
b
a
Vab
FIG. 8.103 Problem 11.
V2
R1 6.8 k 12 V
+– R2
2.2 k
I2
3 mA
8 mA
V1 + –
FIG. 8.104 Problems 12, 17, 25, and 54.
R3 8 6 V
R2
2
E2
R1
4
4 V E1
R2 3
10 VE 1
R1 4
12 VE 2
R3 12
(a) (b)
11. For the network of Fig. 8.103: a. Convert the voltage source to a current source. b. Reduce the network to a single current source, and determine the voltage V1. c. Using the results of part (b), determine V2. d. Calculate the current I2.
SECTION 8.6 Branch-Current Analysis
12. Using branch-current analysis, find the magnitude and direction of the current through each resistor for the networks of Fig. 8.104.
312  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
NA
*13. Using branch-current analysis, find the current through each resistor for the networks of Fig. 8.105. The resistors are all standard values.
*14. For the networks of Fig. 8.106, determine the current I2 using branch-current analysis, and then find the voltage Vab.
FIG. 8.105 Problems 13, 18, and 26.
R1 5.6 k
30 V
R2
3.3 k
E2
10 VE 1
9 V
E1
6 V
E2
(I) (II)
20 VE 3
R3 2.2 k R2
8.2 k
R3 9.1 k
R4
1.1 k
R1
1.2 k
FIG. 8.106 Problems 14, 19, and 27.
R12 R3 3
R2
5
25 V E1 E3 60 V
6 V
E4
E2
I2
Vab
20 V
a
b
R1 3
R2
4
3 A
6 V
E2
E3I 2
Vab
4 V
a
R4 6 R3 8
I1
b
(I) (II)
*15. For the network of Fig. 8.107: a. Write the equations necessary to solve for the branch currents. b. By substitution of Kirchhoff’s current law, reduce the set to three equations. c. Rewrite the equations in a format that can be solved using third-order determinants. d. Solve for the branch current through the resistor R3.
FIG. 8.107 Problems 15, 20, and 28.
I3
E2 6 VE 1 10 V R4 5 R2 1
R1
2
R3
4
R5
3
PROBLEMS  313
NA
IE
VCC 20 V
RB
270 k
RC
2.2 k
RE 510
IC
8 V
E
C
0.7 V
B
+
–
+ –
–
+
– VCC 20 V
+
IB
*16. For the transistor configuration of Fig. 8.108: a. Solve for the currents IB, IC, and IE using the fact that VBE 0.7 V and VCE 8 V. b. Find the voltages VB, VC, and VE with respect to ground. c. What is the ratio of output current IC to input current IB? [Note: In transistor analysis this ratio is referred to as the dc beta of the transistor (bdc).]
SECTION 8.7 Mesh Analysis (General Approach)
17. Find the current through each resistor for the networks of Fig. 8.104.
18. Find the current through each resistor for the networks of Fig. 8.105. 19. Find the mesh currents and the voltage Vab for each network of Fig. 8.106. Use clockwise mesh currents. 20. a. Find the current I3 for the network of Fig. 8.107 using mesh analysis. b. Based on the results of part (a), how would you compare the application of mesh analysis to the branchcurrent method?
*21. Using mesh analysis, determine the current through the 5- resistor for each network of Fig. 8.109. Then determine the voltage Va.
FIG. 8.108 Problem 16.
FIG. 8.109 Problems 21 and 29.
R1  =  4 3 6
R3  =  5
R5
R2  =  2 E2 16 V12 VE 1 R4
Va
R1
1
5
R5
3
R2
15 V E1 R4 V a R3 6 V E2 1 E3 4 V
(a) (b)
10
314  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
NA
*23. Write the mesh equations for each of the networks of Fig. 8.111, and, using determinants, solve for the loop currents in each network.
R2 3.3 k
E2 3 V
R5 6.8 k
E1 18 V
R1 9.1 k
7.5 k
R4
R3 2.2 k
(I) (II)
R5
4
R4
4
E1
16 V
4
R1 7
R6
E2
12 V
3
R2
R3
E3
15 V
10
FIG. 8.110 Problems 22, 30, and 34.
R1
2
1
R3
8
9 V
6 V
E2
R4
(b)
4
6 V
E1
R2
6.8 k 2.7 k
4.7 k
6 V
1.1 k
22 k
8.2 k 2.2 k
5 V
1.2 k
(a)
FIG. 8.111 Problems 23, 31, and 55.
*24. Using the supermesh approach, find the current through each element of the networks of Fig. 8.112.
FIG. 8.112 Problem 24.
(b)
1
6
20 V
3 A
4
8
8 A
(a)
4
24 V
6
10
6 A
12 V
*22. Write the mesh equations for each of the networks of Fig. 8.110, and, using determinants, solve for the loop currents in each network. Use clockwise mesh currents.
PROBLEMS  315
NA
SECTION 8.8 Mesh Analysis (Format Approach)
25. Using the format approach, write the mesh equations for the networks of Fig. 8.104. Is symmetry present? Using determinants, solve for the mesh currents.
26. a. Using the format approach, write the mesh equations for the networks of Fig. 8.105. b. Using determinants, solve for the mesh currents. c. Determine the magnitude and direction of the current through each resistor.
27. a. Using the format approach, write the mesh equations for the networks of Fig. 8.106. b. Using determinants, solve for the mesh currents. c. Determine the magnitude and direction of the current through each resistor. 28. Using mesh analysis, determine the current I3 for the network of Fig. 8.107, and compare your answer to the solution of Problem 15. 29. Using mesh analysis, determine I5 and Va for the network of Fig. 8.109(b).
30. Using mesh analysis, determine the mesh currents for the networks of Fig. 8.110.
31. Using mesh analysis, determine the mesh currents for the networks of Fig. 8.111.
SECTION 8.9 Nodal Analysis (General Approach)
32. Write the nodal equations for the networks of Fig. 8.113, and, using determinants, solve for the nodal voltages. Is symmetry present?
FIG. 8.113 Problems 32 and 38.
R2 4
R4
2
3 A
I2
R3
5
R1
2
5 A
I1
(a)
R4
5
I2
R3
20 R 1 2 4 A
I1
(b)
R2
4
2 A
316  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
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34. a. Write the nodal equations for the networks of Fig. 8.110. b. Using determinants, solve for the nodal voltages. c. Determine the magnitude and polarity of the voltage across each resistor.
*35. For the networks of Fig. 8.115, write the nodal equations and solve for the nodal voltages.
R28
R3
4
4 A I2
R4 6 R 13 5 A I1
(I)
E
12 V
R2
4
I26 AI 1
(II)
R4
2
R1 5 7 A R3
3
R5 8
FIG. 8.114 Problems 33 and 39.
I1 15 V 3 AE 1
(I)
R1 3
R24
R5
6
R3 7
R4
5
6
R6
2 A
I1
(II)
R1 9
R6
20
R4
20
R5
20
R3 18
R24
E116 V
FIG. 8.115 Problems 35 and 40.
36. a. Determine the nodal voltages for the networks of Fig. 8.116. b. Find the voltage across each current source.
(I) (II)
4 6
2 A
5 A
2
5
2
5 A
9
20 V
2
2
4
2
7
FIG. 8.116 Problems 36 and 41.
33. a. Write the nodal equations for the networks of Fig. 8.114. b. Using determinants, solve for the nodal voltages. c. Determine the magnitude and polarity of the voltage across each resistor.
PROBLEMS  317
NA
40 3 A
16 V
4 A
10
6 2 A 12
(I) (II)
4
24 V
20
FIG. 8.117 Problems 37 and 56.
Rs 6
R5
5
R1
5
10
R3
R4
R2
5
20
6 VE
FIG. 8.118 Problems 42 and 43.
Rs 2 k
R5
36 k
R1
33 k
R4
R2
56 k
5.6 k
24 VE
R3
3.3 k
FIG. 8.119 Problems 44 and 45.
*37. Using the supernode approach, determine the nodal voltages for the networks of Fig. 8.117.
SECTION 8.10 Nodal Analysis (Format Approach)
38. Using the format approach, write the nodal equations for the networks of Fig. 8.113. Is symmetry present? Using determinants, solve for the nodal voltages.
39. a. Write the nodal equations for the networks of Fig. 8.114. b. Solve for the nodal voltages. c. Find the magnitude and polarity of the voltage across each resistor.
40. a. Write the nodal equations for the networks of Fig. 8.115. b. Solve for the nodal voltages. c. Find the magnitude and polarity of the voltage across each resistor.
41. Determine the nodal voltages for the networks of Fig. 8.116. Then determine the voltage across each current source.
SECTION 8.11 Bridge Networks
42. For the bridge network of Fig. 8.118: a. Write the mesh equations using the format approach. b. Determine the current through R5. c. Is the bridge balanced? d. Is Equation (8.4) satisfied?
43. For the network of Fig. 8.118: a. Write the nodal equations using the format approach. b. Determine the voltage across R5. c. Is the bridge balanced? d. Is Equation (8.4) satisfied?
44. For the bridge of Fig. 8.119: a. Write the mesh equations using the format approach. b. Determine the current through R5. c. Is the bridge balanced? d. Is Equation (8.4) satisfied?
318  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
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45. For the bridge network of Fig. 8.119: a. Write the nodal equations using the format approach. b. Determine the current across R5. c. Is the bridge balanced? d. Is Equation (8.4) satisfied?
46. Write the nodal equations for the bridge configuration of Fig. 8.120. Use the format approach.
SECTION 8.12 Y-D (T-p) and D-Y (p-T) Conversions 48. Using a D-Y or Y-D conversion, find the current I in each of the networks of Fig. 8.122.
*47. Determine the current through the source resistor Rs of each network of Fig. 8.121 using either mesh or nodal analysis. Discuss why you chose one method over the other.
FIG. 8.120 Problem 46.
9 V
R1
100 k
R4
100 k
R2
200 k
1 k
R34 mA Rs 1 k I 200 k
FIG. 8.121 Problem 47.
20
10
R2
R5
2 A
Rs
R4
(b)
20 R1
R3
20
10 10 I
R1 2 k
E
(a)
Rs 1 k 2 k R2
10 V R3 2 k 2 k R4
R5
2 k
FIG. 8.122 Problem 48.
20 V
I
2
4
1
(a)
2
3
8 V
I
4.7 k
6.8 k
(b)
1.1 k
6.8 k 6.8 k
PROBLEMS  319
NA
*50. Determine the current I for the network of Fig. 8.124.
*51. a. Replace the T configuration of Fig. 8.125 (composed of 6-k resistors) with a p configuration. b. Solve for the source current Is1.
5 A
I
3 k
3 k 6 k
3 k 2 k
3 k
3 k
FIG. 8.124 Problem 50.
*52. a. Replace the p configuration of Fig. 8.126 (composed of 3-k resistors) with a T configuration. b. Solve for the source current Is.
E1 10 V + –
E2 5 V + –R 3 6 k
R2
6 k
R1
6 k I s1
FIG. 8.125 Problem 51.
E 20 V
R5
Rs 1 k
Is
R4 3 k
R3
3 k
R1 2 k R2 2 k
3 k
FIG. 8.126 Problem 52.
*49. Repeat Problem 48 for the networks of Fig. 8.123.
(a) (b)
400 V
I
4 k
42 V
I
4 k
6 k
4 k
18
6 6
6 18 18
FIG. 8.123 Problem 49.
320  METHODS OF ANALYSIS AND SELECTED TOPICS (dc)
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RT
9 9 9
9
9 9 9
9
ab
c
d
hg
fe
FIG. 8.127 Problem 53.
*53. Using Y-D or D-Y conversions, determine the total resistance of the network of Fig. 8.127.
SECTION 8.14 Computer Analysis
PSpice or Electronics Workbench
54. Using schematics, find the current through each element of Fig. 8.104.
*55. Using schematics, find the mesh currents for the network of Fig. 8.111(a).
*56. Using schematics, determine the nodal voltages for the network of Fig. 8.117(II). Programming Language (C , QBASIC, Pascal, etc.)
57. Given two simultaneous equations, write a program to solve for the unknown variables.
*58. Using mesh analysis and determinants, write a program to solve for both mesh currents of the network of Fig. 8.26 (for any component values).
*59. Using nodal analysis and determinants, write a program to solve for the nodal voltages of the network of Fig. 8.44 (for any component values).
GLOSSARY
Branch-current method A technique for determining the branch currents of a multiloop network. Bridge network A network configuration typically having a diamond appearance in which no two elements are in series or parallel. Current sources Sources that supply a fixed current to a network and have a terminal voltage dependent on the network to which they are applied. Delta (D), pi (p) configuration A network structure that consists of three branches and has the appearance of the Greek letter delta (D) or pi (p). Determinants method A mathematical technique for finding the unknown variables of two or more simultaneous linear equations.

Mesh analysis A technique for determining the mesh (loop) currents of a network that results in a reduced set of equations compared to the branch-current method. Mesh (loop) current A labeled current assigned to each distinct closed loop of a network that can, individually or in combination with other mesh currents, define all of the branch currents of a network. Nodal analysis A technique for determining the nodal voltages of a network. Node A junction of two or more branches in a network. Wye (Y), tee (T) configuration A network structure that consists of three branches and has the appearance of the capital letter Y or T.